Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process

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概要

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• In this study, we have applied a second high-stress contect etch stop layer (CESL) in nickel fully silicide complementary metal–oxide–semiconductor field-effect-transistors (Ni FUSI CMOSFETs) and investigated performance characteristics, such as driving capacity, leakages, low-frequency noise (LF noise), and capacitance–voltage ($C$–$V$) characteristics. In Ni FUSI nMOSFETs, the effect of the second CESL on the improvement of carrier mobility is apparent. However, the second CESL also induces defects and junction leakages, resulting in a high LF noise and a low accumulation capacitance. Since we adopted the tensile-stressed second CESL, which is profitless improving the performance of pMOSFETs (should be compress-stressed) and apparently degrades the devices’ driving capability, leakages, and LF noise of the devices. Furthermore, the FUSI process does not induce apparent damage that increases the gate leakages of both Ni-FUSI nMOSFETs and pMOSFETs.

• 2007-04-30

著者

• Lai Chieh-ming

  Institute Of Microelectronics National Cheng Kung University

• Fang Yean-kuen

  Institute Of Microelectronics National Cheng Kung University

• LIN Chien-Ting

  Institute of Microelectronics, National Cheng Kung University

• Yeh Wen-kuan

  Department Of Electrical Engineering National University Of Kaohsiung

• Lai Chieh-Ming

  Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan 70101, Taiwan, R. O. C.

• Lin Chien-Ting

  Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan 70101, Taiwan, R. O. C.

• Fang Yean-Kuen

  Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan 70101, Taiwan, R. O. C.

関連論文

• Efficient Improvement on Device Performance for sub-90nm CMOSFETs
• An Efficient Mobility Enhancement Engineering on 65nm FUSI CMOSFETs using a Second CESL Process
• Stress Technology Impact on Device Performances and Reliability for Sub-90nm Silicon-on-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (Special Issue: Solid State Devices & Materials)
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application
• Mobility Modulation Technology Impact on Device Performance and Reliability for sub-90nm SOI CMOSFETs
• The Impact of Body-Potential on Hot-Carrier-Induced Device Degradation for 90nm Partially-Depleted SOI nMOSFETs
• Width Effect on Hot-Carrier-Induced Degradation for 90nm Partially Depleted SOI CMOSFETs
• Width Effect on Hot-Carrier-induced Degradation for 90nm Partially Depleted SOI CMOSFET
• The Impact of Pad Test-Fixture for De-embedding on Radio-Frequency MOSFETs
• Extra bonus on transistor optimization with stress enhanced notched-gate technology for sub-90nm complementary metal oxide semiconductor field effect transistor (Special issue: Solid state devices and materials)
• Efficient mobility enhancement engineering on 65nm fully silicide complementary metal-oxide-semiconductor field-effect-transistors using second contect etch stop layer process (Special issue: Solid state devices and materials)
• Investigation and Modeling of Stress Interactions on 90nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches (Special Issue: Solid State Devices & Materials)
• An Efficient Improvement for Barrier Effect of W-Filled Contact
• Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor
• New Observations on Hot-Carrier Degradation in 0.1 μm Silicon-on-Insulator n-Type Metal Oxide Semiconductor Field Effect Transistors : Semiconductors
• The Reliability Characteristics of Wafer-Level Chip-Scale Package under Various Current Stressing
• Embedded Process and Characterization Analysis of Discrete Capacitor in Organic-Base Substrate
• Impacts of Layout Dimensions and Ambient Temperatures on Silicon Based On-Chip RF Interconnects
• Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process
• A Study of Relationship of Wafer Breakage vs. Wafer Edge Analysis
• Elucidating the Effects of Current Stress History on Reliability Characteristics by Dynamic Analysis
• Narrow Width and Length Dependence of SiGe and Sallow-Trench-Isolation Stress Induced Defects in 45 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Strained SiGe Source/Drain
• Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress
• Stress Technology Impact on Device Performances and Reliability for $\langle100\rangle$ Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors
• Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs
• Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor
• Low-Frequency Noise in Partially Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures
• Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering
• An Efficient Improvement for Barrier Effect of W-filled Contact
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for Complementary Metal Oxide Semiconductor Radio Frequency Integrated Circuits Applications

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