Impact of 180nm Current Controlled MCML for Realizing Stable Circuit Operations under Threshold Voltage Fluctuations(Session8A: Si Devices III)

スポンサーリンク

概要

• 論文の詳細を見る

• We propose Current Controlled MOS Current Mode Logic (CC-MCML) and have succeeded in fabricating CC-MCML with 180nm CMOS technology for the first time. The performance stability of the CC-MCML inverter on the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔV_B. The ΔV_B, that is defined as (base voltage of output waveform)-(base voltage of input waveform), is a key design parameter because CC-MCML is one type of differential circuit. It is shown that when the threshold voltage of NMOS fluctuates from -70mV to 50mV, and threshold voltage of PMOS fluctuates from -60mV to 60mV, the CC-MCML technique is able to suppress ΔV_B within only 45mV where as the conventional MCML technique caused a maximum ΔV_B of 395mV. In this paper, it is verified for the first time that the proposed CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.

• 社団法人電子情報通信学会の論文
• 2008-07-02

著者

• ENDOH Tetsuo

  Center for Interdisciplinary Research, Tohoku University

• Kamiyanagi Masashi

  Center for Interdisciplinary Research, Tohoku University

• Norifusa Yuto

  Center for Interdisciplinary Research, Tohoku University

• Endoh Tetsuo

  Center For Interdisciplinary Research Tohoku University

• Norifusa Yuto

  Center For Interdisciplinary Research Tohoku University

• Endoh Tetsuo

  Tohoku Univ. Sendai‐shi Jpn

• Koyanagi Mitsumasa

  Dept. Of Bioengineering And Robotics Graduate School Of Engineering Tohoku University

• Kamiyanagi Masashi

  Center For Interdisciplinary Research Tohoku University

• Koyanagi Mitsumasa

  Dept. Of Bioengineering And Robotics Tohoku University

関連論文

• Impact of floating body type DRAM with the vertical MOSFET (Silicon devices and materials)
• Impact of floating body type DRAM with the vertical MOSFET (Electron devices)
• Study on impurity distribution dependence of electron-dynamics in vertical MOSFET (Silicon devices and materials)
• Evaluation of 1/f noise characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET (Electron devices)
• Study on impurity distribution dependence of electron-dynamics in vertical MOSFET (Electron devices)
• Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
• Study on Quantum Electro-Dynamics in Vertical MOSFET
• Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET(Session 7A : Gate Oxides)
• The Analysis of Temperature Dependency of the Mobility In High-k/Metal Gate MOSFET and the Performance on its CMOS Inverter(Session 7A : Gate Oxides)
• The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure.(Session 8A : Memory 2)
• The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure.(Session 8A : Memory 2)
• Verification of Stable Circuit Operation of 180nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation(Session 7B : Si IC and Circuit Technology)
• The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-speed Operation(Session 7B : Si IC and Circuit Technology)
• The Analysis of Temperature Dependency of the Mobility In High-k/Metal Gate MOSFET and the Performance on its CMOS Inverter(Session 7A : Gate Oxides)
• Verification of Stable Circuit Operation of 180nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation(Session 7B : Si IC and Circuit Technology)
• The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-speed Operation(Session 7B : Si IC and Circuit Technology)
• Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor(Session 9B : Nano-Scale devices and Physics)
• Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET(Session 7A : Gate Oxides)
• Impact of Floating Body type DRAM with the Vertical MOSFET(Session 8A : Memory 2)
• Impact of Floating Body type DRAM with the Vertical MOSFET(Session 8A : Memory 2)
• Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET(Session 9B : Nano-Scale devices and Physics)
• Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET(Session 9B : Nano-Scale devices and Physics)
• Over 1GHz High-Speed Current Pulse Generation Circuit for Novel Nonvolatile Memory Cells(Session 7B : Si IC and Circuit Technology)
• Over 1GHz High-Speed Current Pulse Generation Circuit for Novel Nonvolatile Memory Cells(Session 7B : Si IC and Circuit Technology)
• New Magnetic Nano-Dot Memory with FePt Nano-Dots
• Fabrication and Evaluation of Magnetic Tunnel Junction with MgO Tunneling Barrier
• New Magnetic Flash Memory with FePt Magnetic Floating Gate
• Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor(Session 9B : Nano-Scale devices and Physics)
• Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot
• Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot
• Study on Quantum Electro-Dynamics in Vertical MOSFET
• Characteristics of Metal Gate GOI-MOSFET with High-k Gate Dielectric Fabricated by Ge Condensation Method
• Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot
• Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
• Design of 30nm FinFETs and Double Gate MOSFETs with Halo Structure
• Design of 30nm FinFET with Halo Structure
• Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
• Design of 30nm FinFET with Halo Structure
• Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
• Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism(Session5A: Si Devices II)
• Future High Density Memory with Vertical Structured Device Technology
• Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits
• Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit
• Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML type D-Flip Flop(Session8A: Si Devices III)
• Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML type D-Flip Flop(Session8A: Si Devices III)
• New Reconfigurable Memory Architecture for Parallel Image Processing LSI with Three-Dimensional Structure
• Development of Power Supply System for Three-Dimensionally Staked Retinal Prosthesis Chip
• Tungsten Through-Si Via (TSV) Technology for Three-Dimensional LSIs
• Memory Window Enhancement of MOS Memory Devices with High Density Self-Assembled Tungsten Nano-dot
• Development of Si Long Microprobe (SiLM) for Platform of Intelligent Neural Implant Microsystem
• Evaluation of Electrical Stimulus Current to Retina Cells for Retinal Prosthesis by Using Platinum-Black (Pt-b) Stimulus Electrode Array
• Sub-Atmospheric Chemical Vapor Deposition Process for Chip-to-Wafer 3-Dimensional Integration
• Evaluation of Electrical Stimulus Current to Retina Cells for Retinal Prosthesis
• Intelligent Neural Implant Microsystem Fabricated Using Multi-Chip Bonding Technique
• Ultimate Functional Multi-Electrode System (UFMES) Based on Multi-Chip Bonding Technique
• Retinal Prosthesis System with Telemetry Circuit Controlled by Human Eyelid Movement
• Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor(Session5A: Si Devices II)
• Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor(Session5A: Si Devices II)
• Impact of 180nm Current Controlled MCML for Realizing Stable Circuit Operations under Threshold Voltage Fluctuations(Session8A: Si Devices III)
• Impact of 180nm Current Controlled MCML for Realizing Stable Circuit Operations under Threshold Voltage Fluctuations(Session8A: Si Devices III)
• Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism(Session5A: Si Devices II)
• Deep Trench Etching for Chip-to-Chip Three-Dimensional Integration
• New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super Chip Integration
• Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique
• Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices
• Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions
• Enhancing Single-Ion Detection Efficiency by Applying Substrate Bias Voltage for Deterministic Single-Ion Doping
• Temperature Dependence of Electron Tunneling between Two Dimensional Electron Gas and Si Quantum Dots
• Collective Tunneling Model in Charge-Trap-Type Nonvolatile Memory Cell
• Effects of Silicon Source Gas and Substrate Bias on the Film Properties of Si-Incorporated Diamond-Like Carbon by Radio-Frequency Plasma-Enhanced Chemical Vapor Deposition
• Nickel Germanide Formation on Condensed Ge Layer for Ge-on-Insulator Device Application
• Epitaxial Growth of GaN Films by Pulse-Mode Hot-Mesh Chemical Vapor Deposition
• Current Controlled MOS Current Mode Logic with Auto-detection of Threshold Voltage Fluctuation
• Current Controlled MOS Current Mode Logic with Auto-detection of Threshold Voltage Fluctuation
• Study on Quantum Electro-Dynamics in Vertical MOSFET
• The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal–Oxide–Semiconductor Circuits
• Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit
• Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET
• Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65nm CMOS Process
• The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation
• Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor
• Verification of Stable Circuit Operation of 180nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation
• Wave Packet Dynamics in the Spin Torque Transfer
• Study on Quantum Electro-Dynamics in Vertical MOSFET
• Fabrication Method of Sub-100 nm Metal-Oxide-Semiconductor Field-Effect Transistor with Thick Gate Oxide
• Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate
• Role of Synthetic Ferrimagnets in Magnetic Tunnel Junctions from Wave Packet Dynamics
• Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory
• Time-Resolved Switching Characteristic in Magnetic Tunnel Junction with Spin Transfer Torque Write Scheme
• Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation
• Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating
• A Schmitt Trigger Based SRAM with Vertical MOSFET
• High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction
• Source/Drain Engineering for High Performance Vertical MOSFET
• Multi-Electron Wave Packet Dynamics in Applied Electric Field
• Future High Density Memory with Vertical Structured Device Technology
• Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme
• Low Frequency Noise Characterization in Metal Oxide Semiconductor Field Effect Transistor Based Charge Transfer Device at Room and Low Temperatures
• Influence of Coulomb Blockade on Wave Packet Dynamics in Nanoscale Structures
• Fabrication of a Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations for Greedy Power-Reduced Logic Applications

もっと見る 閉じる

スポンサーリンク