Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
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概要
- 論文の詳細を見る
The excellent performance of the 10nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSIs in the sub-10nm generation.
著者
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Yasuda Yukio
Center For Interdisciplinary Research Tohoku University:jst Crest
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ENDOH Tetsuo
Center for Interdisciplinary Research, Tohoku University
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SAKUI Koji
Center for Interdisciplinary Research, Tohoku University
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