Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism(Session5A: Si Devices II)
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, the device performances of sub-10nm Vertical MOSFETs are investigated. One of the drawbacks of conventional planar MOSFETs is that in the sub-10nm generation, its cutoff leakage current increases due to the short channel effects, but even more, its driving current decreases due to the quantum mechanical confinement effects such as the sub-band effect and the depletion of the inversion layer. It is shown for the first time that by downscaling the silicon pillar diameter from 20nm to 4nm, the Vertical MOSFET increases its driving current per footprint to about 2 times and suppresses its total cutoff leakage current per footprint to less than 1/60 at the same time. Moreover, the mechanisms of these improvements of Vertical MOSFET performances are clarified. The results of this work show that Vertical MOSFETs can overcome the drawbacks of conventional planar MOSFETs and achieve the high device performance through the sub-10nm generation.
- 社団法人電子情報通信学会の論文
- 2008-07-02
著者
-
ENDOH Tetsuo
Center for Interdisciplinary Research, Tohoku University
-
Norifusa Yuto
Center for Interdisciplinary Research, Tohoku University
-
Endoh Tetsuo
Center For Interdisciplinary Research Tohoku University
-
Norifusa Yuto
Center For Interdisciplinary Research Tohoku University
関連論文
- Impact of floating body type DRAM with the vertical MOSFET (Silicon devices and materials)
- Impact of floating body type DRAM with the vertical MOSFET (Electron devices)
- Study on impurity distribution dependence of electron-dynamics in vertical MOSFET (Silicon devices and materials)
- Evaluation of 1/f noise characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET (Electron devices)
- Study on impurity distribution dependence of electron-dynamics in vertical MOSFET (Electron devices)
- Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
- Study on Quantum Electro-Dynamics in Vertical MOSFET
- Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET(Session 7A : Gate Oxides)
- The Analysis of Temperature Dependency of the Mobility In High-k/Metal Gate MOSFET and the Performance on its CMOS Inverter(Session 7A : Gate Oxides)
- The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure.(Session 8A : Memory 2)
- The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure.(Session 8A : Memory 2)
- Verification of Stable Circuit Operation of 180nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation(Session 7B : Si IC and Circuit Technology)
- The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-speed Operation(Session 7B : Si IC and Circuit Technology)
- The Analysis of Temperature Dependency of the Mobility In High-k/Metal Gate MOSFET and the Performance on its CMOS Inverter(Session 7A : Gate Oxides)
- Verification of Stable Circuit Operation of 180nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation(Session 7B : Si IC and Circuit Technology)
- The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-speed Operation(Session 7B : Si IC and Circuit Technology)
- Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor(Session 9B : Nano-Scale devices and Physics)
- Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET(Session 7A : Gate Oxides)
- Impact of Floating Body type DRAM with the Vertical MOSFET(Session 8A : Memory 2)
- Impact of Floating Body type DRAM with the Vertical MOSFET(Session 8A : Memory 2)
- Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET(Session 9B : Nano-Scale devices and Physics)
- Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET(Session 9B : Nano-Scale devices and Physics)
- Over 1GHz High-Speed Current Pulse Generation Circuit for Novel Nonvolatile Memory Cells(Session 7B : Si IC and Circuit Technology)
- Over 1GHz High-Speed Current Pulse Generation Circuit for Novel Nonvolatile Memory Cells(Session 7B : Si IC and Circuit Technology)
- Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor(Session 9B : Nano-Scale devices and Physics)
- Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot
- Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot
- Study on Quantum Electro-Dynamics in Vertical MOSFET
- Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot
- Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
- Design of 30nm FinFETs and Double Gate MOSFETs with Halo Structure
- Design of 30nm FinFET with Halo Structure
- Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
- Design of 30nm FinFET with Halo Structure
- Sub-10nm Multi-Nano-Pillar Type Vertical MOSFET
- Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism(Session5A: Si Devices II)
- Future High Density Memory with Vertical Structured Device Technology
- Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits
- Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit
- Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML type D-Flip Flop(Session8A: Si Devices III)
- Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML type D-Flip Flop(Session8A: Si Devices III)
- Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor(Session5A: Si Devices II)
- Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor(Session5A: Si Devices II)
- Impact of 180nm Current Controlled MCML for Realizing Stable Circuit Operations under Threshold Voltage Fluctuations(Session8A: Si Devices III)
- Impact of 180nm Current Controlled MCML for Realizing Stable Circuit Operations under Threshold Voltage Fluctuations(Session8A: Si Devices III)
- Scalability of Vertical MOSFETs in Sub-10nm generation and its Mechanism(Session5A: Si Devices II)
- Fabrication of Silicon Pillar with 25 nm Half Pitch Using New Multiple Double Patterning Technique
- Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices
- Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions
- Enhancing Single-Ion Detection Efficiency by Applying Substrate Bias Voltage for Deterministic Single-Ion Doping
- Temperature Dependence of Electron Tunneling between Two Dimensional Electron Gas and Si Quantum Dots
- Collective Tunneling Model in Charge-Trap-Type Nonvolatile Memory Cell
- Effects of Silicon Source Gas and Substrate Bias on the Film Properties of Si-Incorporated Diamond-Like Carbon by Radio-Frequency Plasma-Enhanced Chemical Vapor Deposition
- Epitaxial Growth of GaN Films by Pulse-Mode Hot-Mesh Chemical Vapor Deposition
- Current Controlled MOS Current Mode Logic with Auto-detection of Threshold Voltage Fluctuation
- Current Controlled MOS Current Mode Logic with Auto-detection of Threshold Voltage Fluctuation
- Study on Quantum Electro-Dynamics in Vertical MOSFET
- The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal–Oxide–Semiconductor Circuits
- Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit
- Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET
- Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65nm CMOS Process
- The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation
- Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor
- Verification of Stable Circuit Operation of 180nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation
- Wave Packet Dynamics in the Spin Torque Transfer
- Study on Quantum Electro-Dynamics in Vertical MOSFET
- Fabrication Method of Sub-100 nm Metal-Oxide-Semiconductor Field-Effect Transistor with Thick Gate Oxide
- Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate
- Role of Synthetic Ferrimagnets in Magnetic Tunnel Junctions from Wave Packet Dynamics
- Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory
- Time-Resolved Switching Characteristic in Magnetic Tunnel Junction with Spin Transfer Torque Write Scheme
- Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation
- Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating
- A Schmitt Trigger Based SRAM with Vertical MOSFET
- High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction
- Source/Drain Engineering for High Performance Vertical MOSFET
- Multi-Electron Wave Packet Dynamics in Applied Electric Field
- Future High Density Memory with Vertical Structured Device Technology
- Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme
- Low Frequency Noise Characterization in Metal Oxide Semiconductor Field Effect Transistor Based Charge Transfer Device at Room and Low Temperatures
- Influence of Coulomb Blockade on Wave Packet Dynamics in Nanoscale Structures
- Fabrication of a Magnetic Tunnel Junction-Based 240-Tile Nonvolatile Field-Programmable Gate Array Chip Skipping Wasted Write Operations for Greedy Power-Reduced Logic Applications