Study of Nickel Silicide Thermal Stability Using Silicon-on-Insulator Substrate for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transisor Device

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概要

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• The thermal stability of nickel silicide (NiSi) on a silicon-on-insulator (SOI) substrate after postsilicidation annealing (550–700 °C) is discussed in this paper. Nickel silicide technology, used for nanoscale complementary metal oxide semiconductor (CMOS) field-effect transistor (FET) devices, has a fundamental problem of thermal stability. Three different Pd concentrations in Ni–Pd alloy, 1, 5, and 10 at. %, were used to study the thermal stability of nickel silicide formed by a silicidation process. The Ni–Pd (10%) sample showed good thermal stability upon annealing at temperatures up to 700 °C for 30 min. Only a low-resistivity mononickel silicide (NiSi) phase peak was observed by X-ray diffraction (XRD) measurement, which was confirmed by Auger electron spectroscopy (AES) analysis. Uniformly formed nickel silicide with a good interface profile was obtained using the Ni–Pd (10%) sample according to field-emission scanning electron microscopy (FE-SEM) measurement. However, the Ni–Pd (5%) sample produced high-resistivity nickel disilicide (NiSi2) after annealing at 650 °C for 30 min. Four different layer structures, Ni, Ni/TiN, Ni/Co/TiN, and Ni–Pd (10%)/Co/TiN, were also used for further study. Among these structures, the Ni–Pd (10%)/Co/TiN layer structure had good thermal stability upon annealing at temperatures up to 700 °C, while the other structures deteriorated due to agglomeration above 550 °C.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2008-10-25

著者

• Lee Hi-deok

  Department Of Electronics Engineering Chungnam National University

• Lee Won-jae

  Department Of Advanced Materials Engineering Dong-eui University

• Kim Ji-young

  Department Of Environmental Engineering Kumoh National Institute Of Technology

• Jeon Hyeongtag

  Division Of Materials Science & Engineering Hanyang University

• Lee Keunwoo

  Division Of Materials Science And Engineering Hanyang University

• Zhang Ying-Ying

  Department of Electronics Engineering, Chungnam National University, 220 Gung-dong, Yuseong-gu, Daejeon 305-764, Korea

• Jung Soon-Yen

  Department of Electronics Engineering, Chungnam National University, 220 Gung-dong, Yuseong-gu, Daejeon 305-764, Korea

• Kim Cho-Rong

  Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University, Obang-dong, Gimhae, Gyeongnam 621-749, Korea

• Lee Jaeyeop

  Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University, Obang-dong, Gimhae, Gyeongnam 621-749, Korea

• Park Won-Wook

  Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University, Obang-dong, Gimhae, Gyeongnam 621-749, Korea

• Ryu Hyukhyun

  Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University, Obang-dong, Gimhae, Gyeongnam 621-749, Korea

• Kim In-Kyum

  R&D Center, Siltron Inc., 283 Imsoo-dong, Gumi, Gyeongbuk 730-724, Korea

• Kang Suk-June

  R&D Center, Siltron Inc., 283 Imsoo-dong, Gumi, Gyeongbuk 730-724, Korea

• Yuk Hyung-Sang

  R&D Center, Siltron Inc., 283 Imsoo-dong, Gumi, Gyeongbuk 730-724, Korea

• Jeon Sunyeol

  Division of Materials Science and Engineering, Hanyang University, Seoul 133-791, Korea

• Leem Jae-Young

  Department of Nano Systems Engineering, Center for Nano Manufacturing, Inje University, Gimhae 621-749, Republic of Korea

• Lee Won-Jae

  Department of Electronics Engineering, Chungnam National University, Gung-dong, Yuseong-gu, Daejeon 305-764, Korea

• Park Won-Wook

  Department of Nano System Engineering, Inje University, Gimhae, Gyeongnam 621-749, Republic of Korea

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