Performance and Stability Characterization of Bottom Gated Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Grown by RF and DC Sputtering
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概要
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In this paper, the performance and the gate bias stability of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with different channel sputtering conditions, RF and DC are studied. DC devices show excellent electrical characteristics but larger charge trapping and slower detrapping in relaxation period under the same gate bias stress. To understand the cause of stress behavior, traps are extracted by subthreshold slop and low-high frequency dependent capacitance measurement and compared before and after gate bias stress. The extracted trap densities well explain the process-dependent device properties like as threshold voltage, mobility and on/off current ratio, but are not dependent on bias stress. From current–voltage ($I$–$V$) and capacitance–voltage ($C$–$V$) measurement, we can conclude that the threshold voltage instability arises due to the process of temporary charge trapping which is dominant only at gate bias stress and the trapping/detrapping behavior is strongly dependent on the channel layer deposition condition.
- 2009-04-25
著者
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Lee Hi-deok
Department Of Electronics Engineering Chungnam National University
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Lee Ga-won
Department Of Electrical Engineering Korea Advanced Institute Of Science And Technology
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Choi Won-Ho
Department of Physiology and Anesthesiology, College of Medicine, Institute of Biomedical Science and Technology, Konkuk University
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Park Sung-Soo
Department of Electronics Engineering, Chungnam National University, 220 Gung-dong, Yuseong-gu, Daejeon 305-764, Republic of Korea
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Lee Hi-Deok
Department of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea
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Nam Dong-Ho
Department of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea
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Chai Kwang-il
Department of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea
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Jeong Jae-Kyeong
Corporate R and D Center, Samsung SDI Co., Ltd., 428-5 Gongse-dong, Kiheung-gu, Yongin, Gyeonggi-do 449-902, Korea
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Choi Won-Ho
Department of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea
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Choi Won-Ho
Department of Electronics Engineering, Chungnam National University, 220 Gung-dong, Yuseong-gu, Daejeon 305-764, Republic of Korea
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Park Sung-Soo
Department of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea
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Choi Won-Ho
Department of Computer Engineering, University of Kyungnam
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