Improvement of the Reliability of a Cu/W–N/SiOF Multilevel Interconnect by Inserting Plasma Enhanced Chemical Vapor Deposited W–N Thin Film
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概要
- 論文の詳細を見る
We have investigated the characteristics of a Cu/W–N/SiOF multilevel interconnect. The resistivity and surface roughness of the Cu film on a W–N/SiOF/Si substrate are better than those of the Cu film on a SiOF/Si substrate after annealing at 500$^\circ$C for 30 min. These results are due to the W–N thin film inserted between the Cu and SiOF because the surface energy of the W–N film is greater than that of the SiOF film, which improves the wettability of Cu on the W–N film and prevents the agglomeration of the Cu film during the annealing process. Also, the stress evolution, current–voltage ($I$–$V$) characteristics and Rutherford backscattering (RBS) spectra reveal that the Cu/W–N/SiOF/Si interconnect has lower tensile stress and better electrical properties than the Cu/SiOF/Si interconnect, which is due to the stress relaxation and the improvement of the barrier performance as a result of inserting the W–N thin films.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 2001-03-15
著者
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Kim Seong-il
Semiconductor Devices Laboratory Korea Institute Of Science And Technology
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Kim Yong
Semiconductor Devices Laboratory Korea Institute Of Science And Technology
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Park Jong-wan
Division Of Materials Science And Engineering Hanyang University
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Lee Seoghyeong
Division Of Materials Science And Engineering Hanyang University
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Sim Hyun
Semiconductor Devices Laboratory Korea Institute Of Science And Technology
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Kim Dong
Semiconductor Lab, Samsung Advanced Institute of Technology, Samsung Electronics, Gyeonggi-do 446-712, Korea
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Park Jong-Wan
Division of Materials Science and Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-ku, Seoul 133-791, Korea
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Sim Hyun
Semiconductor Materials Laboratory, Korea Institute of Science and Technology, P.O. Box 131, Cheongryang, Seoul 136-791, Korea
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Lee Seoghyeong
Division of Materials Science and Engineering, Hanyang University, 17 Haengdang-dong, Seongdong-ku, Seoul 133-791, Korea
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Kim Dong
Semiconductor Materials Laboratory, Korea Institute of Science and Technology, P.O. Box 131, Cheongryang, Seoul 136-791, Korea
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