ED2000-66 / SDM2000-66 Improvement of Memory windows in YMnO_3/Si Ferroelectric Gate FET
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概要
- 論文の詳細を見る
YMnO_3/Si ferroelectric gates have been prepared with different Y/Mn composition ratios. For the YMnO_3 that has the Y/Mn ratio of 1.2-1.4/l memory window of the ferroelectric gate is so great as 4.8 V at 5 V. In contrast, if the Y/Mn ratio is 1.5-2.2/l the memory window is only 0.2 V at the same gate bias. Improvement in the memory window is due to the c-axis oriented (0001) YMnO_3 grown on (111) Y_2O_3 thin layer that is formed by the reaction of Y atoms and oxygen between the YMnO_3 and native oxide during rapid thermal annealing process. A peripheral circuit is designed for read/write operation of NDRO-FRAM memory cell organized with Pt/YMnO_3/Y_2O_3/Si FETs.
- 社団法人電子情報通信学会の論文
- 2000-06-22
著者
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Park Young
Korea Institute Of Science And Technology
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KIM Ik-Soo
Korea Electrotechnology Research Institute
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Kim Yong
Korea University College Of Medicine
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Kim Y
Kist Seoul Kor
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Kim Y‐h
Semiconductor Devices Laboratory Korea Institute Of Science And Technology
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Kim Ik-soo
Korea Institute Of Science And Technology
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Kim Yong
Semiconductor Devices Laboratory Korea Institute Of Science And Technology
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Park Young
Korea Institute Of Energy Research
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Kim Yong
Korea Institute Of Science And Technology
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Kim Yong
Korea Atomic Energy Research Inst.
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Park Young
Korea Electric Power Research Institute
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Kim Yong
Korea Atomic Energy Res. Inst.
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