Fabrication of Low Line Edge Roughness Mold for Photo-Nanoimprint
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概要
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We attempted to fabricate patterns having low line edge roughness (LER) by photo-nanoimprint for evaluation of critical dimension (CD) atomic-force microscopy (AFM). In order to fabricate the transparent low LER mold, we used spin on glass (SOG) imprinted using a low LER Si master mold made by anisotropic wet etching. We investigated SOG imprint properties as a function of pattern size. For patterns less than 0.5 μm wide, we formed the patterns on SOG having the same depth as the corresponding pattern height on the mold. Detailed observation showed that patterns broadened for outermost lines in line-and-space patterns where the Si master mold was not pushed perpendicularly into the SOG layer. We fabricated patterns on SOG molds 180 nm high and 100 nm wide and having a 200 nm period. Photo-nanoimprint was carried out using the SOG mold, and the LER of patterns on a photocurable polymer was 0.74 nm, comparable to that of the Si master mold.
- 2004-06-15
著者
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NAMATSU Hideo
NTT LSI Laboratories
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Taniguchi Jun
Department Of Applied Electronics Tokyo University Of Science
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Miyamoto Iwao
Department Of Applied Electronics Tokyo University Of Science
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KURASHIMA Yuichi
MIRAI, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Scie
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HIROSHIMA Hiroshi
MIRAI, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Scie
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KIM Sang
MIRAI, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Scie
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Yamazaki Naoto
Department Of Applied Electronics Tokyo University Of Science
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Matsui Shinji
Laboratory Of Advanced Science And Technolgy For Industory Himeji Institute Of Technology
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Komuro Masanori
MIRAI Project, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Komuro Masanori
MIRAI, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Kim Sang
MIRAI, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Kurashima Yuichi
MIRAI Project, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Hiroshima Hiroshi
MIRAI Project, Advanced Semiconductor Research Center (ASRC), National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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Taniguchi Jun
Department of Applied Electronics, Tokyo University of Science, 2641 Yamazaki, Noda, Chiba 278-8510, Japan
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