Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process
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概要
- 論文の詳細を見る
A stochastic signal detection circuit that uses a non-linearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500MS/s.
著者
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Taniguchi Kenji
Department Of Biotechnology Tottori University
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Wang Jun
Department Of Automation And Computer-aided Engineering The Chinese University Of Hong Kong
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Matsuoka Toshimasa
Department of Electrical, Electronic and Information Engineering, Osaka University
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Ham Hyunju
Department of Electrical, Electronic and Information Engineering, Osaka University
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