A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD (Special Section of Papers Selected from ITC-CSCC'96)

概要

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To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "0" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8μ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.
社団法人電子情報通信学会の論文
1997-06-25