A Low Power Analog Matched-Filter with Smart Sliding Correlation
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概要
- 論文の詳細を見る
A low power analog matched filter circuit with smart sliding correlation is proposed for direct sequence code division multiple access (DS-CDMA) despreading process. The influence of level shifter mismatch on the trade-off between speed, power and resolution of the analog correlator circuit is investigated with respect to technology scaling. The optimization in power, acquisition time and areal efficiency is considered. Simulation with code length of 127 reveals that the analog matched filter circuit provides good linearity, and dissipates only 22 mW at a voltage supply of 3.3 V and an operational clock frequency of 128 MHz, using 0.35 μm CMOS technology.
- 社団法人 電気学会の論文
- 2003-11-01
著者
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TANIGUCHI Kenji
Department of Cancer Research, Fuji Gotemba Research Laboratories, Chugai and Pharmaceutical Co
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Matsuoka Toshimasa
Department Of Electronic Engineering Osaka University
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Matsuoka T
Osaka Univ. Osaka Jpn
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Matsuoka Toshimasa
The Graduate School Of Engineering Osaka University
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SHIMIZU Shinsaku
Graduate School of Engineering, Osaka University
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ELTOKHY Mostafa
Department of Electronics and Information Systems, Osaka University
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Taniguchi K
Department Of Electronics And Information Systems Osaka University
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Taniguchi K
Division Of Electrical Electronics And Information Engineering Graduate School Of Engineering Osaka
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Taniguchi K
Kyushu Univ.
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SHIMIZU Shinsaku
Department of Electronics and Information Systems, Osaka University
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Eltokhy Mostafa
Department Of Electronics And Information Systems Osaka University
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Shimizu Shinsaku
Graduate School Of Engineering Osaka University
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Taniguchi Kenji
Department Of Biotechnology Tottori University
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Matsuoka Toshimasa
Department of Electrical, Electronic and Information Engineering, Osaka University
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