Experimental Evidence of Carrier Depletion Effect near n^+Poly-Si Gate Side Wall/SiO_2 Interfaces for Sub-100nm nMOSFETs

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概要

• 論文の詳細を見る
• 社団法人電子情報通信学会の論文
• 2001-06-28

著者

• Hirose Masataka

  Advanced Semiconductor Research Center National Institute Of Advanced Industrial Science And Technol

• MURAKAMI Hideki

  Department of Geology, Faculty of Science, Kochi University

• Miyazaki S

  Graduate School Of Advanced Sciences And Matters Hiroshima University

• Murakami Hideki

  Department Of Electrical Engineering Graduate School Of Advanced Sciences Of Matter Hiroshima Univer

• MIHARA Tatsuyoshi

  Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima Univ

• Yamashita Hiroki

  Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima Univ

• Miyazaki Siichi

  Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima Univ

• Yamashita Hiroki

  Department Of Electrical Engineering Graduate School Of Advanced Sciences Of Matter Hiroshima Univer

• Mihara Tatsuyoshi

  Department Of Electrical Engineering Graduate School Of Advanced Sciences Of Matter Hiroshima Univer

• Miyazaki Seiichi

  Graduate School Of Advanced Sciences And Matters Hiroshima University

• Miyazaki Siichi

  Department Of Electrical Engineering Graduate School Of Advanced Sciences Of Matter Hiroshima Univer

• YAMASHITA Hideo

  Faculty of Engineering Hiroshima University

• Yamashita H

  Hiroshima Univ Higashihiroshima

• Hirose Masataka

  Department Of Electrical Engineering Graduate School Of Advanced Sciences Of Matter Hiroshima Univer

• Miyazaki Seiichi

  Graduate School Of Engineering Nagoya University

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