Suguro Kyoichi | Toshiba Corporation Semiconductor Company

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概要

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著作論文

Sub-1.3 nm Amorphous Tantalum Pentoxide Gate Dielectrics for Damascene Metal Gate Transistors
Sub 1.3nm Amorphous Ta_2O_5 Gate Dielectrics for Damascene Metal Gate Transistor
Highly Uniform Low-Pressure Chemical Vapor Deposition (LP-CVD) of Si_3N_4 Film on Tungsten for Advanced Low-Resistivity "Polymetal" Gate Interconnects
Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 μm MOSFETs
Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs
Ultrashallow Junction Formation for Sub-100nm Complementary Metal-Oxide-Semiconductor Field-Effect Transistor by Controlling Transient Enhanced Diffusion
Improved Ti Self-Aligned Silicide Technology Using High Dose Ge Pre-Amorphization for 0.10 μm CMOS and Beyond
Reduction in PN Junction Leakage for Ni-silicided Small Si Islands by Using Thermal Conduction Heating with Stacked Hot Plates
Low Leakage TiO_2 Gate Insulator Formed by Ultrathin TiN Deposition and Low-Temperature Oxidation
Reliable High-k TiO_2 Gate Insulator Formed by Ultrathin TiN Deposition and Low Temperature Oxidation
Novel Elevated Source/Drain Technology for FinFET Overcoming Agglomeration and Facet Problems Utilizing Solid Phase Epitaxy
Highly Uniform Deposition of LP-CVD 3i3N4 Films on Tungsten for Advanced Low Resistivity "Poly-Metal" Gate Interconnects
Correlation of W-Si-N Film Microstructure with Barrier Performance against Cu Diffusion
Correlation of W-Si-N Film Microstructure with Barrier Performance against Cu Diffusion
Inlaid Cu Interconnects Employing Ti-Si-N Barrier Metal for ULSI Applications
10-15nm Ultrashallow Junction Formation by Flash-Lamp Annealing
New Finding of Pt Segregation at the NiSi/Si Interface by Atom Probe

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