Tsunashima Y | Process And Manufacturing Engineering Center Semiconductor Company Toshiba Corporation

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著作論文

Sub-1.3 nm Amorphous Tantalum Pentoxide Gate Dielectrics for Damascene Metal Gate Transistors
Sub 1.3nm Amorphous Ta_2O_5 Gate Dielectrics for Damascene Metal Gate Transistor
Mechanism of Defect Formation during Low-Temperature Si Epitaxy on Clean Si Substrate
Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping (VPD)
Dominant Factor for the Concentration of Phosphorus Introduced by Vapor Phase Doping
Novel Elevated Source/Drain Technology for FinFET Overcoming Agglomeration and Facet Problems Utilizing Solid Phase Epitaxy
Retarding Mechanism of Si Selective Epitaxial Growth on CMOS Structure due to Doped Arsenic in the Si Substrate
Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow Shallow Trench Isolation
Facet-Free Si Selective Epitaxial Growth Adaptable to Elevated Source/Drain MOSFETs with Narrow STI

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