Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories

スポンサーリンク

概要

• 論文の詳細を見る

• We propose an ultrathin body silicon nanocrystal memory with a large threshold voltage shift ($\Delta V_{\text{th}}$) and a small write/erase threshold voltage ($V_{\text{th}}$) distribution. Experimental results show that $\Delta V_{\text{th}}$ increases when body thickness decreases to 6 nm. Although $\Delta V_{\text{th}}$ also increases in an ultranarrow channel, the ultrathin-body memory has a much smaller write/erase $V_{\text{th}}$ distribution than the ultranarrow-channel memory. It is confirmed by simulation that a large $\Delta V_{\text{th}}$ in an ultranarrow channel originates from a larger increase in the potential of a thin body than in that of a thick body.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-04-15

著者

• YANAGIDAIRA Kosuke

  Graduate School of Science and Engineering, Chuo University

• Saitoh Masumi

  Institute Of Industrial Science University Of Tokyo

• HIRAMOTO Toshiro

  Institute Industrial Science, The University of Tokyo

関連論文

• Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors
• Room Temperature Coulomb Blockade and Low Temperature Hopping Transport in a Multiple-Dot-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor ( Quantum Dot Structures)
• Fabrication of Si Nanostructures for Single Electron Device Applications by Anisotropic Etching
• Modeling of Body Factor and Subthreshold Swing in Short Channel Bulk MOSFETs
• Very Sharp Room-Temperature Negative Differential Conductance in Silicon Single-Hole Transistor with High Voltage Gain
• Temperature Dependence of Off-Current in Bulk and FD SOI MOSFETs
• High Performance Accumulated Back-Interface Dynamic Threshold SOI MOS-FET's (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations(Device,Low-Power, High-Speed LSIs and Related Technologies)
• Short Channel Characteristics of Variable Body Factor FD SOI MOSFETs
• Future Electron Devices and SOI Technology : Semi-Planar SOI MOSFETs with Sufficient Body Effect
• Evidence for Creation of Gallium Antisite Defect in Surface Region of Bleat-Treated GaAs
• Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots
• Characteristic Distributions of Narrow Channel Metal-Oxide-Semiconductor Field-Effect Transistor Memories with Silicon Nanocrystal Floating Gates
• Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories
• Large Threshold Voltage Shift and Narrow Threshold Voltage Distribution in Ultra Thin Body Silicon Nanocrystal Memories
• Optimum Condutions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs
• Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs
• Measurement of Energetic and Lateral Distribution of Interface State Density in Fully-Depleted Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• High-Performance Accumulated Back-Interface Dynamic Threshold SOI MOSFET (AB-DTMOS) with Large Body Effect at Low Supply Voltage
• Measurement of Energetic and Lateral Distribution of Interface State Density in FD SOI MOSFETs
• Suppression of Geometric Component of Charge Pumping Current in Thin Film Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• Extremely Large Amplitude of Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures
• Origin of Critical Substrate Bias in Variable Threshold Voltage Complementary MOS (VTCMOS)
• Origin of Critical Substrate Bias in Variable Threshold Voltage CMOS
• Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation
• Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS(DOT-MTCMOS)
• Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature Operating Silicon Single-Hole Transistor
• Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors
• Room-Temperature Demonstration of Low-Voltage Static Memory Based on Negative Differential Conductance in Silicon Single-Hole Transistors
• Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime
• Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal–Oxide–Semiconductor Field-Effect Transistors
• Evaluation of Threshold-Voltage Variation in Silicon on Thin Buried Oxide Complementary Metal–Oxide–Semiconductor and Its Impact on Decreasing Standby Leakage Current
• Wide-Range Threshold Voltage Controllable Silicon on Thin Buried Oxide Integrated with Bulk Complementary Metal Oxide Semiconductor Featuring Fully Silicided NiSi Gate Electrode
• Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors (Special Issue : Solid State Devices and Materials (1))
• Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors
• Large Temperature Dependence of Coulomb Blockade Oscillations in Room-Temperature-Operating Silicon Single-Hole Transistor
• Room-Temperature Operation of Current Switching Circuit Using Integrated Silicon Single-Hole Transistors
• Temperature Dependence of Off-Current in Bulk and Fully Depleted SOI MOSFETs
• On the Origin of Negative Differential Conductance in Ultranarrow-Wire-Channel Silicon Single-Electron and Single-Hole Transistors
• Superior $\langle 110\rangle$-Directed Electron Mobility to $\langle 100\rangle$-Directed Electron Mobility in Ultrathin Body (110) n-Type Metal–Oxide–Semiconductor Field-Effect Transistors
• Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)
• Impact of Drain Induced Barrier Lowering on Read Scheme in Silicon Nanocrystal Memory with Two-Bit-per-Cell Operation
• Room-Temperature Observation of Negative Differential Conductance Due to Large Quantum Level Spacing in Silicon Single-Electron Transistor
• Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method
• Extremely Large Amplitude Random Telegraph Signals in a Very Narrow Split-Gate MOSFET at Low Temperatures
• Experimental Study on the Universality of Mobility Behavior in Ultra Thin Body Metal Oxide Semiconductor Field Effect Transistors
• Experimental Study on Mobility in (110)-Oriented Ultrathin-Body Silicon-on-Insulator n-Type Metal Oxide Semiconductor Field-Effect Transistor with Single- and Double-Gate Operations
• Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors
• Reverse Short-Channel Effect of Body Factor in Low-Fin Field-Effect Transistors Induced by Corner Effect
• Silicon Single-Hole Transistor with Large Coulomb Blockade Oscillations and High Voltage Gain at Room Temperature
• Effects of Side Surface Roughness on Carrier Mobility in Tri-Gate Single Silicon Nanowire Metal--Oxide--Semiconductor Field-Effect Transistors
• Short-Channel Characteristics of Variable-Body-Factor Fully-Depleted Silicon-On-Insulator Metal–Oxide–Semiconductor-Field-Effect-Transistors
• Large Electron Addition Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor
• Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress
• Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs
• NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM
• Tunneling Barrier Structures in Room-Temperature Operating Silicon Single-Electron and Single-Hole Transistors
• Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots
• Future Electron Devices and SOI Technology —Semi-Planar SOI MOSFETs with Sufficient Body Effect—
• Measurement of Energetic and Lateral Distribution of Interface State Density in Fully-Depleted Silicon on Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors (Special Issue : Solid State Devices and Materials)
• Integration of Complementary Metal-Oxide-Semiconductor 1-Bit Analog Selectors and Single-Electron Transistors Operating at Room Temperature (Special Issue : Solid State Devices and Materials)
• Effects of Channel Thinning on Threshold Voltage Shift in Ultrathin-Body Silicon Nanocrystal Memories

もっと見る 閉じる

スポンサーリンク