擬似SoC技術を用いた集積型MEMS-半導体マイクロチップの開発

概要

論文の詳細を見る
The authors have developed pseudo-SoC technology to realize MEMS-LSI integrated micro-chip. The pseudo-SoC technology consists of three technologies which are wafer reconfiguration technology, inter-chip redistribution layer technology, and pseudo-SoC thinning technology. In the wafer reconfiguration technology, the filling of resin and surface step between heterogeneous chips were improved through the optimization of vacuum printing process and resin material. These improvements reduced the warpage of reconfiguration wafer, leading to achievement of the reconfiguration wafer with 5 inch in diameter. In the inter-chip redistribution layer technology, the interface adherence between planar layer and inter-chip redistribution layer was improved, leading to the inter-chip redistribution layer with 1μm/1μm in line/space on reconfiguration wafer. In the pseudo-SoC thinning technology, thin pseudo-SoC device with 100μm in thickness was achieved through developing mechanical backside grinding process technology. Furthermore, ultra-thin pseudo-SoC which integrated electrostatic MEMS light valve and PWM driver IC was prototyped through developing the ultra-thin MEMS encapsulation technology.