4327 積層フリップ実装構造チップ内の残留応力分布(J05-3 実装信頼性,J05 電子情報機器,電子デバイスの熱制御と強度・信頼性評価)

概要

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We performed a finite element analysis in order to make clear the residual stress distribution in stacked chips mounted by flip chip technology using area array metallic bumps. The maximum value of the normal stress changes about 200MPa by changing the assembly structure from a wire bonding structure to a flip chip structure. The amplitude of the local stress of about 90MPa also appears between two bumps. The residual stress in the stacked two chips varies depending on the distance from a bending neutral axis of the stacked structure. In addition, the local stress distribution between two bumps was confirmed by using a stress sensor chip that includes about 160 strain gauges with 10-μm length.
一般社団法人日本機械学会の論文
2006-09-15