Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer

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概要

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• WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at \pm 7 V were 300 μs and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application.

• 2012-06-25

著者

• Cho Won-ju

  Department Of Electronic Material Engineering Kwangwoon University

• Lee Hyo

  Department Of Chemical Engineering Konkuk University

• Kim Eun

  Department Of Anesthesia And Pain Medicine School Of Medicine Pusan National University

• Lee Dong

  Department Of Aerospace Engineering Chonbuk National University

• Kim Eun

  Department of Physics and Research Institute for Natural Sciences, Hanyang University, Seoul 133-791, Republic of Korea

• You Hee-Wook

  Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Republic of Korea

• You Hee-Wook

  Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Korea

• Cho Won-Ju

  Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Republic of Korea

• KIM Eun

  Department of Agricultural Biotechnology, Seoul National University

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