Channel Recessed One Transistor Dynamic Random Access Memory with SiO2/Si3N4/SiO2 Gate Dielectric
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概要
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A fully depleted (FD) single-transistor dynamic random-access memory (1T-DRAM) cell with SiO2--Si3N4--SiO2 (ONO) stacked gate dielectric was fabricated on a recessed silicon channel. The electrical and memory characteristics of a 1T-DRAM with a stacked ONO gate dielectric were compared with those of 1T-DRAM cell with a single SiO2 gate insulator. As a result, the FD channel recessed 1T-DRAM cell with an ONO gate insulator provides excellent electrical characteristics such as a high on/off ratio of nearly 10^{9} and a low leakage current ({<}10^{-14} A). Further, the sensing margin of channel recessed 1T-DRAM cells was largely enhanced by the ONO stacked gate insulator compared to a single SiO2 layer at the same operation condition.
- 2012-06-25
著者
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Cho Won-ju
Department Of Electronic Material Engineering Kwangwoon University
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Yang Jong-Heon
Biosensor Research Team, BT Convergence Technology Research Department, IT Convergence Technology Research Laboratory, ETRI, Daejeon 305-350, Korea
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Park Jin-Kwon
Department of Electronic Materials Engineering, Kwangwoon University, Seoul 139-701, Korea
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