Quantitative Examination of Mobility Lowering Associated with Ultrathin Gate Oxides in Silicon Metal-Oxide-Semiconductor Inversion Layer
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概要
- 論文の詳細を見る
In this study, mobility lowering inherent to ultrathin gate oxides is experimentally examined in the silicon metal-oxide-semiconductor (Si MOS) inversion layer, and additional scattering mechanisms associated with gate oxide scaling are discussed, paying attention to the extraction of reliable experimental data on inversion-layer mobility. It is found that poly-Si-gate impurity concentration strongly affects the mobility lowering associated with ultrathin gate oxides, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. This finding indicates the contribution of remote Coulomb scattering due to the gate impurities. In addition, low-temperature measurements reveal that roughness scattering is enhanced, possibly because of the poor Si/SiO2 interface in the initial stage of oxide growth. Therefore, further gate oxide scaling down to 1.5 nm or less can cause remote Coulomb scattering as well as enhanced roughness scattering, resulting in the saturation or decrease in the drive current capability.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-04-15
著者
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Koga Junji
Advanced Lsi Technology Laboratory Corporate R & D Center Toshiba Corporation
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Ishihara Takamitsu
Advanced Lsi Technology Laboratory Corporate Research & Development Center
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Takagi Shin-ichi
Advanced Lsi Technology Laboratory Corporate Research & Development Center Toshiha Corporation
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Takagi Shin-ichi
Advanced LSI Technology Laboratory, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Koga Junji
Advanced LSI Technology Laboratory, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Ishihara Takamitsu
Advanced LSI Technology Laboratory, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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