Low Gate-Induced Drain Leakage and Its Physical Origins in Si Nanowire Transistors
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概要
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Gate-induced drain leakage (GIDL) in Si nanowire transistors fabricated on silicon-on-insulator substrates is systematically studied. In narrow nanowire transistors, GIDL current is obtained by relatively small potential difference between the gate and the drain due to the superior electrostatic control by gate voltage. On the other hand, variation of GIDL current with gate voltage is drastically reduced in nanowire transistors with the wire width of around 10 nm, which realizes devices with extremely small off-current. The reduction of local electric field around the drain junction due to low impurity concentration in source/drain extensions and the relatively large source/drain parasitic resistance are identified as the main mechanisms of small GIDL current.
- 2011-04-25
著者
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Numata Toshinori
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Saitoh Masumi
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Ishihara Takamitsu
Advanced Lsi Technology Laboratory Corporate Research & Development Center
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Nakabayashi Yukio
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Nakabayashi Yukio
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Numata Toshinori
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Zaitsu Koichiro
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Zaitsu Koichiro
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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