Enhanced Degradation by Negative Bias Temperature Stress in Si Nanowire Transistor
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概要
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Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.
- 2012-02-25
著者
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Numata Toshinori
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Saitoh Masumi
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Tanaka Chika
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Nakabayashi Yukio
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Uchida Ken
Department Of Biology Faculty Of Science Kumamoto University
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Ota Kensuke
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Numata Toshinori
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Ota Kensuke
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Tanaka Chika
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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Saitoh Masumi
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
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