Stress and Surface Orientation Engineering in Scaled CMOSFETs Considering High-Field Carrier Transport(Session 4A : Channel Engineering)
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概要
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We present the systematic study on the performance of short-channel and strained (100) and (110) n/pMOSFETs. Saturation drain current (I_<dsat>) of short-channel (110) nFETs approaches (100) nFETs as a result of strong velocity saturation in (100) nFETs. Meanwhile, I_<dsat> of short-channel (110) pFETs are still superior to (100) pFETs due to weaker velocity saturation than nFETs. Carrier velocity (ν) and I_<dsat> increase by strain is determined not only by low-field mobility (μ) enhancement (Δμ/μ) but also by the modulation of saturation velocity (ν_<sat>). It is found that ν_<sat> increases more by strain in smaller-Δμ/μ devices. As a result, Δν/ν of (100)/(110) n/pFETs converge in sub-30nm regime, because the difference of Δμ/μ is compensated by ν_<sat> change. The superiority of (110) CMOS to (100) CMOS is maintained at highly-strained conditions.
- 2010-06-23
著者
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SAITOH Masumi
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation
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NAKABAYASHI Yukio
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation
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UCHIDA Ken
Tokyo Institute of Technology
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NUMATA Toshinori
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation
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Numata Toshinori
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Saitoh Masumi
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Nakabayashi Yukio
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Saitoh Masumi
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation
関連論文
- Stress and Surface Orientation Engineering in Scaled CMOSFETs Considering High-Field Carrier Transport(Session 4A : Channel Engineering)
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