Experimental Study on Performance Improvement in Dopant-Segregated Schottky Metal–Oxide–Semiconductor Field-Effect Transistors
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概要
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Factors that underlie the performance improvement of dopant-segregated Schottky (DSS) metal–oxide–semicondutor field-effect transistors (MOSFETs) compared with conventional (Conv.) MOSFETs are examined experimentally. Three factors are compared for DSS and Conv. MOSFETs; namely, effective junction depth, the hot carrier effect, and parasitic resistance. We found that all the following factors are associated with performance improvement in DSS MOSFETs: shallower junction depth, higher impact ionization rate, and lower parasitic resistance. It is considered that the shallower junction depth and lower parasitic resistance respectively contribute to the better short-channel-effect immunity and higher drive current of the DSS MOSFETs. The higher impact ionization rate is consistent with the higher carrier injection velocity, which is another factor of the drive current enhancement. We focus on the reduction of parasitic resistance and compare the components of the parasitic resistances of DSS and Conv. MOSFETs to analyze the factors of the reduction of parasitic resistance. We also speculate on the effectiveness of the parasitic resistance reduction in DSS FETs as high-performance devices for future LSIs.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2008-01-25
著者
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Koga Junji
Advanced Lsi Technology Laboratory Corporate R & D Center Toshiba Corporation
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Nishi Yoshifumi
Advanced Lsi Technology Laboratory Corporate R&d Center Toshiba Corporation
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Kinoshita Atsuhiro
Advanced Lsi Technology Laboratory Corporate R & D Center Toshiba Corporation
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Kinoshita Atsuhiro
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Nishi Yoshifumi
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Hagishima Daisuke
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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Hagishima Daisuke
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522, Japan
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