"Mask Enhancer" Technology on ArF Immersion Tool for 45-nm-Node Complementary Metal Oxide Semiconductor with 0.249μm^2 Static Random Access Memory Contact Layer Fabrication
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2006-06-30
著者
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Matsuo Taku
The Department Of Computer Science And Electronics Kyushu Institute Of Technology
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Endo M
Department Of Physics School Of Science Tokai University
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Matsuo T
Matsushita Electric Industrial Co. Ltd. (panasonic)
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Matsuo T
The Author Is With The Tr Production Division Rohm-apollo Device Co. Ltd.
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YUITO Takashi
Matsushita Electric Industrial Co., Ltd. (Panasonic)
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WIAUX Vincent
IMEC vzw
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VAN LOOK
IMEC vzw
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VANDENBERGHE Geert
IMEC vzw
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IRIE Shigeo
Matsushita Electric Industrial Co., Ltd. (Panasonic)
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MATSUO Takahiro
Matsushita Electric Industrial Co., Ltd. (Panasonic)
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MISAKA Akio
Matsushita Electric Industrial Co., Ltd. (Panasonic)
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ENDO Masayuki
Matsushita Electric Industrial Co., Ltd. (Panasonic)
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SASAGO Masaru
Matsushita Electric Industrial Co., Ltd. (Panasonic)
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Irie S
Semiconductor Leading Edge Technologies Ibaraki Jpn
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Sasago M
Assoc. Super‐advanced Electronics Technol. Yokohama Jpn
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