Novel Gate-Recess Process for the Reduction of Parasitic Phenomena Due to Side-Etching in InAlAs/InGaAs HEMTs

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概要

• 論文の詳細を見る
• 1997-09-16

著者

• ENOKI Takatomo

  NTT System Electronics Laboratories

• SUEMITSU Tetsuya

  NTT System Electronics Laboratories

• YOKOYAMA Haruki

  NTT System Electronics Laboratories

• ISHII Yasunobu

  NTT System Electronics Laboratories

• Ishii Y

  Waseda Univ. Tokyo Jpn

• Enoki Takatomo

  Ntt Photonics Laboratories

• Yokoyama H

  Kddi R&d Laboratories Inc.

• Ishii Y

  Yamaguchi Univ. Ube‐shi Jpn

• Suemitsu T

  Ntt Photonics Lab. Kanagawa Jpn

関連論文

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• W-Band Active Integrated Antenna Oscillator Based on Full-Wave Design Methodology and 0.1-μm Gate InP-Based HEMTs(Millimeter-Wave Devices,Heterostructure Microelectronics with TWHM2005)
• Monolithic integration of UTC-PDs and InP HBTs using Be ion implantation
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• Design Methods for Utility Max-Min Fair Share Networks(Network)
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• Accurate Evaluation of Silicon Planar Doping in InAlAs for InAlAs/InGaAs Modulation Doped Structure Grown by Metal Organic Chemical Vapor Deposition
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• Novel Gate-Recess Process for the Reduction of Parasitic Phenomena Due to Side-Etching in InAlAs/InGaAs HEMTs
• A Fully Monolithic Integrated 43-Gbit/s Clock and Data Recovery Circuit Using InAlAs/InGaAs/InP HEMTs
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• Gate and Recess Engineering for Ultrahigh-Speed InP-Based HEMTs (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
• High-Resolution Scanning Electron Microscopy Observation of Electrochemical Etching in the Formation of Gate Grooves for InP-Based Modulation-Doped Field-Effect Transistors
• InP-based High-speed Transistors and Their IC Applications
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• Electroluminescence from am Inlays-Based High Electron Mobility Transistor Designed for High-Speed Operation
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• Suppression of short-channel effect in pseudomorphic In0.25Al0.75P/In0.75Ga0.25As high electron mobility transistors

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