Effects of Base Oxide Thickness and Silicon Composition on Charge Trapping in HfSiO/SiO2 High-$k$ Gate Stacks
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概要
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This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-$k$ gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf–OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-$k$ gate stacks.
- 2005-08-15
著者
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Chen Shih-chang
Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company
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CHEN Mao-Chieh
Department of Electronics Engineering & The Institute of Electronics, National Chiao Tung University
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Liang Mong-song
Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company
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Tsui Bing-yue
Department Of Electronics Engineering & Institute Of Electronics National Chiao Tung University
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Jin Yin
Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company
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Tao Hun-jan
Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company
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Hou Yong-tian
Advanced Module Technology Division Taiwan Semiconductor Manufacturing Company
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Wu Wei-hao
Department Of Electronics Engineering And Institute Of Electronics National Chiao-tung University
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Wu Wei-Hao
Department of Electronics Engineering, National Chiao Tung University, 1001, Ta-Hsueh Road, Hsin-Chu 300, Taiwan, R.O.C.
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Chen Mao-Chieh
Department of Electronics Engineering, National Chiao Tung University, 1001, Ta-Hsueh Road, Hsin-Chu 300, Taiwan, R.O.C.
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Tsui Bing-Yue
Department of Electronics Engineering, National Chiao Tung University, 1001, Ta-Hsueh Road, Hsin-Chu 300, Taiwan, R.O.C.
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Liang Mong-Song
Advanced Module Technology Division, Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Road VI, Science-Based Industrial Park, Hsin-Chu 300, Taiwan, R.O.C.
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Yao Liang-Gi
Advanced Module Technology Division, Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Road VI, Science-Based Industrial Park, Hsin-Chu 300, Taiwan, R.O.C.
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Hou Yong-Tian
Advanced Module Technology Division, Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Road VI, Science-Based Industrial Park, Hsin-Chu 300, Taiwan, R.O.C.
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Chen Shih-Chang
Advanced Module Technology Division, Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Road VI, Science-Based Industrial Park, Hsin-Chu 300, Taiwan, R.O.C.
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Tao Hun-Jan
Advanced Module Technology Division, Taiwan Semiconductor Manufacturing Company, No. 8, Li-Hsin Road VI, Science-Based Industrial Park, Hsin-Chu 300, Taiwan, R.O.C.
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