2-bit Arithmetic Logic Unit Utilizing Hexagonal BDD Architecture for Implementation of Nanoprocessor on GaAs Nanowire Network(Session4B: Emerging Devices II)

概要

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2-bit arithmetic logic unit (ALU) utilizing the binary-decision diagram (BDD) logic architecture for nanoprocessor is fabricated on GaAs hexagonal nanowire networks with Schottky wrap gates (WPGs) and their operation is characterized. The ALU integrates 32 node devices and implements 4 instructions. They are fabricated by 3M or 16M nodes/cm^2 fabrication processes. Fabricated ALU shows correct operations experimentally obtained in classical transport domain at room temperature. Supply voltage and input voltage swing dependences of the circuit operation are characterized. Discrete node devices are also investigated from viewpoint of integration, including path switching, threshold voltage variation and gate leakage current.
社団法人電子情報通信学会の論文
2008-07-02