Characterization of Corner-Induced Leakage Current of a Shallow Silicided n^+/p Junction for Quarter-Micron MOSFETs

スポンサーリンク

概要

著者

関連論文

Trade-Off between Hot Carrier Effect and Current Driving Capability Due to Drain Contact Structures in Deep Submicron MOSFETs
Effects of Low Temperature Interlayer Dielectric Films on the Gate Oxide Quality of Deep Submicron MOSFET's
Effects of Low Temperature Interlayer Dielectric Films on the Gate Oxide Quality of Deep Submicron MOSFET's
New Observation of NBTI Degradation and Recovery Effect of Plasma Nitrided Oxide in Nano Scale PMOSFET's
Temperature effects on silicon-oxide-nitride-oxide-silicon transistors under channel hot electron injection operation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Temperature effects on silicon-oxide-nitride-oxide-silicon transistors under channel hot electron injection operation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Low Temperature Formation of Highly Thermal Immune Ni Germanosilicide Using NiPt Alloy with Co Over-layer in Si_Ge_x according to Different Ge Fractions (x)
Characterization of the Co-Silicide Penetration Depth into the Junction Area for 0.15 and Sub-0.15 Micron CMOS Technology
Defects study of retrograde twin well CMOS that has MeV ion implanted buried layer
Defects study of retrograde twin well CMOS that has MeV ion implanted buried layer
Analysis of Transfer Gate in CMOS Image Sensor(Session 6A : TFTs and Sensors)
Ramping Amplitude Multi-Frequency Charge Pumping Technique for Silicon-Oxide-Nirtride-Oxide-Silicon Flash EEPROM Cell Transistors
Characterization of Corner Induced Leakage Current in Shallow Silicided n^+/p Junction
Characterization of the Co-Silicide Penetration Depth into the Junction Area
Highly Thermal Immune Ni GermanoSilicide with Nitrogen-Doped Ni and Co/TiN Double Capping Layer for Nano-Scale CMOS Applications
Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology(Si Devices and Processes, Fundamental and Application of Advanced Semiconductor Devices)
Novel Nitrogen doped Ni SALICIDE Process for Nano-Scale CMOS Technology
Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology
Study of Abnormal Oxidation of Ni-Germanosilicide by High Temperature Post-Silicidation Annealing(Session A3 Si Materails and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Study of Abnormal Oxidation of Ni-Germanosilicide by High Temperature Post-Silicidation Annealing(Session A3 Si Materails and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
Shallow Trench Isolation Characteristics with High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide for Deep-Submicron CMOS Technologies
Dependence of Subthreshold Hump and Reverse Narrow Channel Effect on the Gate Length by Suppression of Transient Enhanced Diffusion at Trench Isolation Edge
Dependence of Sub-Threshold Hump and RNWE Characteristics on the Gate Length by TED
Dependence of Reverse Narrow Width Effect and Sub-threshold Hump Characteristics on the Gate length
Dependence of Reverse Narrow Width Effect and Sub-threshold Hump Characteristics on the Gate length
Dependence of Reverse Narrow Width Effect and Sub-threshold Hump Characteristics on the Gate length
TaO_xN_y Gate Dielectric with Improved Thermal Stability
Near Surface Oxide Trap Density Profiling in NO and Remote Plasma Nitrided Oxides in Nano-Scale MOSFETs, Using Multi-Temperature Charge Pumping Technique : N_ vs. Oxide Processing
Characterization of Hot Carrier Mechanism of Nano-Scale CMOSFETs(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Characterization of Hot Carrier Mechanism of Nano-Scale CMOSFETs(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation
ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation
Electrical and Optical Characteristics of an a-Si:H/c-Si Heterojunction Switch
Characterization of Corner-Induced Leakage Current of a Shallow Silicided n^+/p Junction for Quarter-Micron MOSFETs
Study of Drain Contact Structure Dependent Deep Submicron MOSFET Reliability by Photon Emission Analysis
Impact of Nitrogen Implantation in Lightly Doped Drain(NIL)on Deep Sub-Micron CMOS Devices
The Impact of Nitrogen Implantation at LDD(NIL) on Deep Sub-Micron CMOS Devices
Control of Boron Lateral Diffusion by Nitrogen Implantation in Sub-0.15mm CMOS Devices
Control of Boron Lateral Diffusion by Nitrogen Implantation in Sub-0.15mm CMOS Devices
Control of Boron Lateral Diffusion by Nitrogen Implantation in Sub-0.15mm CMOS Devices

もっと見る

スポンサーリンク