On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
スポンサーリンク
概要
- 論文の詳細を見る
Interconnect parasitic parameters and their contribution to delay time are extracted on chip environment. Six kinds of test patterns are used to extract each interconnect parameters. The extracted parameters and their contribution to delay time are summarized in a look-up table. The circuit performance can be easily predicted using the look-up table. Moreover, the usefulness of the look-up table in designing repeaters is also shown.
- 社団法人電子情報通信学会の論文
- 1999-07-23
著者
-
Kang Dae-gwan
R&d Division Lg Semicon Co. Ltd.
-
Lee Hi-deok
R&d Division Lg Semicon Co. Ltd.
-
Lee Hi-deok
Advanced Technology Laboratory Lg Semicon Co. Ltd.
-
Lee Hi-deok
Advanced Technology Laboratory. Lg Semicon Co.
-
Jang M‐j
Hynix Semiconductor Co. Choongbuk Kor
-
Hwang J‐m
Hyundai Microelectronics Co. Cheongju Kor
-
Hwang Jeong-mo
Hyundai Electronics Industries Co.ltd. Memory R&d Division
-
Hwang Jeong-mo
R&d Division Lg Semicon Co. Ltd.
-
Hwang Jeong-mo
R&d Division Hyundai Microelectronics Co.
-
Lee Hi-Deok
R&D Division, LG Semicon Co., Ltd.
-
Jang Myoung-Jun
R&D Division, LG Semicon Co., Ltd.
-
Park Myoung-Kyu
R&D Division, LG Semicon Co., Ltd.
-
Kang Dae-Gwan
R&D Division, LG Semicon Co., Ltd.
-
Hwang Jeong-Mo
R&D Division, LG Semicon Co., Ltd.
-
Hwang Jeong-mo
Advan. Tech. Lab. Lg Semicon Co. Ltd.
-
Hwang J.-m.
Hyundai Electronics Industries Co.ltd. Memory R&d Division
-
Lee H‐d
Chungnam National Univ. Taejon Kor
-
Park Myoung-kyu
R&d Division Lg Semicon Co. Ltd.
関連論文
- Trade-Off between Hot Carrier Effect and Current Driving Capability Due to Drain Contact Structures in Deep Submicron MOSFETs
- Effects of Low Temperature Interlayer Dielectric Films on the Gate Oxide Quality of Deep Submicron MOSFET's
- Effects of Low Temperature Interlayer Dielectric Films on the Gate Oxide Quality of Deep Submicron MOSFET's
- New Observation of NBTI Degradation and Recovery Effect of Plasma Nitrided Oxide in Nano Scale PMOSFET's
- Temperature effects on silicon-oxide-nitride-oxide-silicon transistors under channel hot electron injection operation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Temperature effects on silicon-oxide-nitride-oxide-silicon transistors under channel hot electron injection operation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Low Temperature Formation of Highly Thermal Immune Ni Germanosilicide Using NiPt Alloy with Co Over-layer in Si_Ge_x according to Different Ge Fractions (x)
- Characterization of the Co-Silicide Penetration Depth into the Junction Area for 0.15 and Sub-0.15 Micron CMOS Technology
- Analysis of Transfer Gate in CMOS Image Sensor(Session 6A : TFTs and Sensors)
- Ramping Amplitude Multi-Frequency Charge Pumping Technique for Silicon-Oxide-Nirtride-Oxide-Silicon Flash EEPROM Cell Transistors
- Characterization of Corner Induced Leakage Current in Shallow Silicided n^+/p Junction
- Characterization of the Co-Silicide Penetration Depth into the Junction Area
- Highly Thermal Immune Ni GermanoSilicide with Nitrogen-Doped Ni and Co/TiN Double Capping Layer for Nano-Scale CMOS Applications
- Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology(Si Devices and Processes, Fundamental and Application of Advanced Semiconductor Devices)
- Novel Nitrogen doped Ni SALICIDE Process for Nano-Scale CMOS Technology
- Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology
- Study of Abnormal Oxidation of Ni-Germanosilicide by High Temperature Post-Silicidation Annealing(Session A3 Si Materails and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Study of Abnormal Oxidation of Ni-Germanosilicide by High Temperature Post-Silicidation Annealing(Session A3 Si Materails and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
- On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
- On-Chip Extraction of Interconnect Line Induced Delay Time for Quarter and Sub-Quarter Micron CMOS Technology
- Shallow Trench Isolation Characteristics with High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide for Deep-Submicron CMOS Technologies
- TaO_xN_y Gate Dielectric with Improved Thermal Stability
- Near Surface Oxide Trap Density Profiling in NO and Remote Plasma Nitrided Oxides in Nano-Scale MOSFETs, Using Multi-Temperature Charge Pumping Technique : N_ vs. Oxide Processing
- Characterization of Hot Carrier Mechanism of Nano-Scale CMOSFETs(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Characterization of Hot Carrier Mechanism of Nano-Scale CMOSFETs(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation
- ED2000-50 / SDM2000-50 Oxidation Behaviors of Ti-Polycide Gate Stack During Gate Re-oxidation
- Electrical and Optical Characteristics of an a-Si:H/c-Si Heterojunction Switch
- Characterization of Corner-Induced Leakage Current of a Shallow Silicided n^+/p Junction for Quarter-Micron MOSFETs
- Impact of Nitrogen Implantation in Lightly Doped Drain(NIL)on Deep Sub-Micron CMOS Devices
- The Impact of Nitrogen Implantation at LDD(NIL) on Deep Sub-Micron CMOS Devices
- Control of Boron Lateral Diffusion by Nitrogen Implantation in Sub-0.15mm CMOS Devices
- Control of Boron Lateral Diffusion by Nitrogen Implantation in Sub-0.15mm CMOS Devices
- Control of Boron Lateral Diffusion by Nitrogen Implantation in Sub-0.15mm CMOS Devices