An Improvement in Metal-Ferroelectric-Insulator-Semiconductor Structure for Ferroelectric Gate FET Memory Using a Silicon Nitride Buffer Layer

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概要

• 論文の詳細を見る
• 1999-09-20

著者

• 野田 三喜男

  愛知教大

• Noda Minoru

  Area Of Materials And Device Physics Department Of Physical Science Graduate School Of Engineering S

• OKUYAMA Masanori

  Area of Materials and Device Physics, Department of Physical Science, Graduate School of Engineering

• Okuyama Masanori

  Area Of Materials And Device Physics Department Of Physical Science Graduate School Of Engineering S

• Noda M

  Department Of Electronics Fukuoka Institute Of Technology

• Narita Masanao

  Institute Of Space And Astronautical Science Japan Aerospace Exploration Agency

• Sugiyama H

  Data Storage Amp Retrieval Systems Division Hitachi Ltd.

• Adachi Yuji

  Matusita Electric Industrial Co.ltd.

• SUGIYAMA Hideki

  Area of Materials and Device Physics, Department of Physical Science, Graduate School of Engineering

• NAKAISO Toshiyuki

  Area of Materials and Device Physics, Department of Physical Science, Graduate School of Engineering

• ADACHI Yuji

  Area of Materials and Device Physics, Department of Physical Science, Graduate School of Engineering

• Adachi Yuji

  Area Of Materials And Device Physics Department Of Physical Science Graduate School Of Engineering S

• Okuyama M

  Graduate School Of Engineering Science Osaka University

• Nakaiso Toshiyuki

  Area Of Materials And Device Physics Department Of Physical Science Graduate School Of Engineering S

• Okuyama Masanori

  Area of Advanced Electronics and Optical Science, Department of Systems Innovation, Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka, Osaka 560-8531, Japan

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