Sugiyama N | Mirai-association Of Super-advanced Electronics Technology (aset)

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概要

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著作論文

In Situ Characterization of the Initial Growth Stage of GaAs on Si by Coaxial Impact-Collision Ion Scattering Spectroscopy
Real-Time Observation of AlAs/GaAs Superlattice Growth by Coaxial Impact Collision Ion Scattering Spectroscopy
Reduction of Dislocation Density in GaAs on Si Substrate by Si Interlayer and Initial Si Buffer Layer
In Situ Analysis of Gallium Arsenide Surfaces by Coaxial Impact Collision Ion-Scattering Spectroscopy with an Off-Axis Ion Source
Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process
High Mobility Fully-Depleted Germanium-on-Insulator pMOSFET with 32-nm-Thick Ge Channel Layer Formed by Ge-Condensation Technique
Performance Enhancement under High-Temperature Operation and Physical Origin of Mobility Characteristics in Ge-rich strained SiGe-on-Insulator pMOSFETs
Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method
Advanced SOI MOSFET's with Strained-Si/SiGe Heterostructures(Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures
Strained-Si-on-Insulator (Strained-SOI) MOSFETs-Concept, Structures and Device Characteristics
Formation of SiGe on Insulator Structure and Approach to Obtain Highly Strained Si Layer for MOSFETs
A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-on-Insulator MOSFETs
A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100nm Strained Silicon-on-Insulator MOSFETs
Non-Volatile Doubly Stacked Si Dot Memory with Si Nano-Crystalline Layer
Variation of threshold voltage in strained Si metal-oxide-semiconductor field-effect transistors induced by non-uniform strain distribution in strained-Si channels on silicon-germanium-on-insulator substrates
Novel Si Quantum Memory Structure with Self-Aligned Stacked Nanocrystalline Dots
Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
Experimental Analysis of Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory

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