Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-07-15
著者
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Usuda Koji
Mirai-aset
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Mizuno Tomohisa
Mirai-aist
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Takagi S
Mirai-national Institute Of Advanced Industrial Science And Technology (aist)
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MORIYAMA Yoshihiko
MIRAI-Association of Super-Advanced Electronics Technology (ASET)
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SUGIYAMA Naoharu
MIRAI-Association of Super-Advanced Electronics Technology (ASET)
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TEZUKA Tsutomu
MIRAI(ASET)
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NAHAKARA Shu
MIRAI Project, Association of Super-Advanced Electronics Technology (ASET)
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TAKAGI Sin-ichi
MIRAI Project, Association of Super-Advanced Electronics Technology (ASET)
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Nahakara Shu
Mirai-association Of Super-advanced Electronics Technology (aset)
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Sugiyama N
Mirai-association Of Super-advanced Electronics Technology (aset)
関連論文
- In Situ Characterization of the Initial Growth Stage of GaAs on Si by Coaxial Impact-Collision Ion Scattering Spectroscopy
- Real-Time Observation of AlAs/GaAs Superlattice Growth by Coaxial Impact Collision Ion Scattering Spectroscopy
- Reduction of Dislocation Density in GaAs on Si Substrate by Si Interlayer and Initial Si Buffer Layer
- In Situ Analysis of Gallium Arsenide Surfaces by Coaxial Impact Collision Ion-Scattering Spectroscopy with an Off-Axis Ion Source
- Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process
- High Mobility Fully-Depleted Germanium-on-Insulator pMOSFET with 32-nm-Thick Ge Channel Layer Formed by Ge-Condensation Technique
- Performance Enhancement under High-Temperature Operation and Physical Origin of Mobility Characteristics in Ge-rich strained SiGe-on-Insulator pMOSFETs
- Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method
- Advanced SOI MOSFET's with Strained-Si/SiGe Heterostructures(Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
- Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures