Variation of threshold voltage in strained Si metal-oxide-semiconductor field-effect transistors induced by non-uniform strain distribution in strained-Si channels on silicon-germanium-on-insulator substrates
スポンサーリンク
概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
著者
-
HIRASHITA Norio
MIRAI-Association of Super-Advanced Electronics Technology (ASET)
-
Sugiyama N
Mirai-association Of Super-advanced Electronics Technology (aset)
関連論文
- In Situ Characterization of the Initial Growth Stage of GaAs on Si by Coaxial Impact-Collision Ion Scattering Spectroscopy
- Real-Time Observation of AlAs/GaAs Superlattice Growth by Coaxial Impact Collision Ion Scattering Spectroscopy
- Reduction of Dislocation Density in GaAs on Si Substrate by Si Interlayer and Initial Si Buffer Layer
- In Situ Analysis of Gallium Arsenide Surfaces by Coaxial Impact Collision Ion-Scattering Spectroscopy with an Off-Axis Ion Source
- Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process
- High Mobility Fully-Depleted Germanium-on-Insulator pMOSFET with 32-nm-Thick Ge Channel Layer Formed by Ge-Condensation Technique
- Performance Enhancement under High-Temperature Operation and Physical Origin of Mobility Characteristics in Ge-rich strained SiGe-on-Insulator pMOSFETs
- Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method
- Advanced SOI MOSFET's with Strained-Si/SiGe Heterostructures(Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
- Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures
- Strained-Si-on-Insulator (Strained-SOI) MOSFETs-Concept, Structures and Device Characteristics
- Formation of SiGe on Insulator Structure and Approach to Obtain Highly Strained Si Layer for MOSFETs
- A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- Non-Volatile Doubly Stacked Si Dot Memory with Si Nano-Crystalline Layer
- Variation of threshold voltage in strained Si metal-oxide-semiconductor field-effect transistors induced by non-uniform strain distribution in strained-Si channels on silicon-germanium-on-insulator substrates
- Novel Si Quantum Memory Structure with Self-Aligned Stacked Nanocrystalline Dots
- Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
- Experimental Analysis of Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
- Variation of Threshold Voltage in Strained Si Metal–Oxide–Semiconductor Field-Effect Transistors Induced by Non-uniform Strain Distribution in Strained-Si Channels on Silicon–Germanium-on-Insulator Substrates