Formation of SiGe on Insulator Structure and Approach to Obtain Highly Strained Si Layer for MOSFETs
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概要
- 論文の詳細を見る
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 2001-04-01
著者
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Takagi S
Mirai-national Institute Of Advanced Industrial Science And Technology (aist)
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MIZUNO Tomohisa
Advanced LSI Technology Laboratory, Toshiba Corporation
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SUGIYAMA Naoharu
Advanced LSI Technology Laboratory, Toshiba Corporation
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SUZUKI Masamichi
Environmental Engineering & Analysis Center, Corporate R&D Center, Toshiba Corporation
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TAKAGI Sin-ichi
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation
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Sugiyama N
Mirai-association Of Super-advanced Electronics Technology (aset)
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- In Situ Analysis of Gallium Arsenide Surfaces by Coaxial Impact Collision Ion-Scattering Spectroscopy with an Off-Axis Ion Source
- Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process
- High Mobility Fully-Depleted Germanium-on-Insulator pMOSFET with 32-nm-Thick Ge Channel Layer Formed by Ge-Condensation Technique
- Performance Enhancement under High-Temperature Operation and Physical Origin of Mobility Characteristics in Ge-rich strained SiGe-on-Insulator pMOSFETs
- Evaluation of Dislocation Density of SiGe-on-Insulator Substrates using Enhanced Secco Etching Method
- Advanced SOI MOSFET's with Strained-Si/SiGe Heterostructures(Joint Special Issue on Heterostructure Microelectronics with TWHM 2000)
- Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures
- Strained-Si-on-Insulator (Strained-SOI) MOSFETs-Concept, Structures and Device Characteristics
- Formation of SiGe on Insulator Structure and Approach to Obtain Highly Strained Si Layer for MOSFETs
- A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100nm Strained Silicon-on-Insulator MOSFETs
- Non-Volatile Doubly Stacked Si Dot Memory with Si Nano-Crystalline Layer
- Variation of threshold voltage in strained Si metal-oxide-semiconductor field-effect transistors induced by non-uniform strain distribution in strained-Si channels on silicon-germanium-on-insulator substrates
- Novel Si Quantum Memory Structure with Self-Aligned Stacked Nanocrystalline Dots
- Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
- Experimental Analysis of Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
- Formation of SiGe on Insulator Structure and Approach to Obtain Highly Strained Si Layer for MOSFETs