TEZUKA Tsutomu | Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation

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概要

• 同名の論文著者
• Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporationの論文著者

関連著者

• Takagi S

  Mirai-national Institute Of Advanced Industrial Science And Technology (aist)

• MIZUNO Tomohisa

  Advanced LSI Technology Laboratory, Toshiba Corporation

• SUGIYAMA Naoharu

  Advanced LSI Technology Laboratory, Toshiba Corporation

• TAKAGI Shin-ichi

  Advanced LSI Technology Laboratory, Toshiba Corporation

• TEZUKA Tsutomu

  Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation

• Sugiyama N

  Mirai-association Of Super-advanced Electronics Technology (aset)

• Sugiyama N

  Research And Development Center Toshiba Corporation

• Sugiyama Naoharu

  Advanced Lsi Technology Laboratory Research And Development Center Toshiba Corporation

• Takagi Shin-ichi

  Advanced Lsi Technology Laboratory Research & Development Center Toshiba Corporation

• Tezuka T

  Mirai-aset

• Mizuno T

  Nippon Leiz Co. Ltd. Tama‐shi Jpn

• Takagi Shin-ichi

  Advanced Lsi Technology Laboratory Corporate Research & Development Center Toshiha Corporation

• Tezuka Tsutomu

  Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 1 Komukai-Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan

• MIZUNO Tomohisa

  Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation

• SUZUKI Masamichi

  Environmental Engineering & Analysis Center, Corporate R&D Center, Toshiba Corporation

• Suzuki Masamichi

  Environmental Engineering And Analysis Center Corporate Research & Development Center Toshiba Co

• Mizuno Tomohisa

  Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan

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著作論文

• Novel Fabrication Technique for Relaxed SiGe-on-Insulator Substrates without Thick SiGe Buffer Structures
• A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-on-Insulator MOSFETs
• A Novel Fabrication Technique of Ultra-Thin and Relaxed SiGe Buffer Layers with High Ge Content for Sub-100nm Strained Silicon-on-Insulator MOSFETs

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