Counter Dipole Layer Formation in Multilayer High-k Gate Stacks
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概要
- 論文の詳細を見る
Dipole layer formation at the high-k/SiO2 interface is now recognized to be the dominant origin of threshold voltage (V_{\text{TH}}) shift in metal gate high-k complementary metal--oxide--semiconductor (CMOS) devices, although the dipole formation mechanism is still controversial. Whatever the mechanism is, the dipole effect is practically used for V_{\text{TH}} tuning in the band-edge metal/high-k gate stack CMOS. The optimum conditions may be found by changing the material and/or process conditions, but there is still a missing fact in the high-k/SiO2 dipole formation experiment. It is the dipole cancelling effect (counter dipole formation) in SiO2/high-k/SiO2/Si gate stacks, where the dipole effect in principle should disappear owing to the formation of two dipoles in opposing directions. In this paper, we report our experimental results on the counter dipole effect and then discuss the interface characteristics between two different high-k layers as well.
- 2012-08-25
著者
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Kita Koji
Department Of Materials Engineering School Of Engineering The University Of Tokyo
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Toriumi Akira
Department Of Applied Physics University Of Tokyo
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Nagashio Kosuke
Department Of Materials Engineering The University Of Tokyo
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Nishimura Tomonori
Department Of Chemistry Faculty Of Science Okayama University
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Hibino Shinya
Department of Materials Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Kita Koji
Department of Material Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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