New Reconfigurable Memory Architecture for Parallel Image-Processing LSI with Three-Dimensional Structure
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概要
- 論文の詳細を見る
A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a $9\times9$ filtering operation.
- 2008-04-25
著者
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Sugimura Takeaki
Department Of Bioengineering And Robotics Graduate School Of Engineering Tohoku University
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Fukushima Takafumi
Department Of Advanced Materials Chemistry Graduate School Of Engineering Yokohama National Universi
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Tanaka Tetsu
Department Of Quantum Materials Science University Of Tokushima
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Kodama Shigeo
Department Of Bioengineering And Robotics Graduate School Of Engineering Tohoku University
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Koyanagi Mitsumasa
Department Of Bioengineering And Robotics Graduate School Of Engineering Tohoku University
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Amano Daijirou
Department of Bioengineering and Robotics, Tohoku University, 6-6-01 Aza Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
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Tanaka Tetsu
Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University, 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
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Kodama Shigeo
Department of Bioengineering and Robotics, Tohoku University, 6-6-01 Aza Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan
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