New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

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概要

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• A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In–Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm2 and ranging in thickness from 30 to 90 μm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2006-04-30

著者

• Yamada Yusuke

  Department Of Chemical Engineering Faculty Of Engineering Kyushu University

• Fukushima Takafumi

  Department Of Advanced Materials Chemistry Graduate School Of Engineering Yokohama National Universi

• KIKUCHI Hirokazu

  Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University

• Koyanagi Mitsumasa

  Department Of Bioengineering And Robotics Graduate School Of Engineering Tohoku University

• Yamada Yusuke

  Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University, 6-6-01 Aza Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan

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