A Power-Down Circuit Scheme Using Data-Preserving Complementary Pass Transistor Flip-Flop for Low-Power High-Performance Multi-Threshold CMOS LSI(Electronic Circuits)

概要

論文の詳細を見る
A new power-down circuit scheme using data-preserving complementary pass transistor flip-flop circuit for low-power, high-performance Multi-Threshold voltage CMOS (MTCMOS) LSI is presented. The proposed circuit can preserve a stored data during power-down period while maintaining low leakage current without any extra circuit and complex timing design. The flip-flop provides 24% improved delay and 30% less silicon area compared to conventional MTCMOS flip-flop circuit. A 16-bits DSP processor core using the proposed circuit and 0.18μm CMOS technology was designed. The DSP chip was successfully operated at 120 MHz, 1.65 V and its total leakage current in power-down mode was four orders smaller than conventional DSP chip.
社団法人電子情報通信学会の論文
2004-04-01