Improvement of Contact Resistance between Ru Electrode and TiN Barrier in Ru/Crystalline-Ta_2O_5/Ru Capacitor for 50nm Dynamic Random Access Memory
スポンサーリンク
概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-04-30
著者
-
Lim Han-jin
Semiconductor R&d Center Samsung Electronics Co.
-
Lim Han-jin
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Moon Joo-tae
Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
CHUNG U-In
Process Development Thani, Semiconductor R&D Division, Sam suns Uectronics Co., Ltd.
-
YOO Cha-Young
Process Development Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
KIM Sung-Tae
Process Development Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
LIM HanJin
Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co. Ltd.
-
CHUNG Suk-Jin
Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co. Ltd.
-
LEE Kwang
Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co. Ltd.
-
LEE Jinil
Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co. Ltd.
-
KIM Jin
Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co. Ltd.
-
Chung Suk-jin
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Kim Sung-tae
Advanced Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Lee Jinil
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Lee Kwanghee
Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Yoo Cha-young
Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Kim S‐t
Samsung Electronics Co. Ltd. Gyeonggi‐do Kor
-
Kim Sung-tae
Process Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Moon Joo-tae
Process Development Team Memory Division Samsung Electronics Co. Ltd.
-
Chung U-in
Process Development Team Memory Division Samsung Electronics Co. Ltd.
-
Yoo Cha-young
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Yoo Chayoung
Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Kim Jin
Advanced Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Kim Jin
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Lee Kwang
Process Development Team Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Lim Hanjin
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
関連論文
- Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes
- Integration of Ferroelectric Random Access Memory Devices with Ir/IrO_2/Pb(Zr_xTi_)O^^_3/Ir Capacitors Formed by Metalorganic Chemical Vapor Deposition-Grown Pb(Zr_xTi_)O_3
- Enhanced Retention Characteristics of Pb(Zr, Ti)O_3 Capacitors by Ozone Treatment : Electrical Properties of Condensed Matter
- Performance and Reliability of MIM (Metal-Insulator-Metal) Capacitors with ZrO_2 for 50nm DRAM Application
- Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance
- Improvement of Contact Resistance between Ru Electrode and TiN Barrier in Ru/Crystalline-Ta_2O_5/Ru Capacitor for 50nm Dynamic Random Access Memory
- Improvement of Contact Resistance of Ru electrode/TiN barrier at Ru/Crystalline-Ta_2O_5/Ru Capacitor for 50nm DRAM device
- Investigation of CVD-Co Silicidation for the Improvement of Contact Resistance
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
- Electrical Properties of Crystalline Ta_2O_5 with Ru Electrode
- Electrical Properties of Ru/Ta_2O_5/Ru Capacitor for 1 Giga-Scale DRAMs and Beyond
- The Electrical Properties of Concave-type (Ba,Sr) TiO_3 Capacitors for Advanced Memories
- The Electrical Properties of Concave-type (Ba,Sr) TiO_3 Capacitors for Advanced Memories
- The Electrical Properties of Concave-type (Ba,Sr) TiO_3 Capacitors for Advanced Memories
- Effects of the Deposition Conditions of the Seed Layer on the Crystallinity and Electrical Characteristics of the Pb(Zr, Ti)O_3 Films
- Effect of Activation of Oxygen by Electron Cyclotron Resonance Plasma on the Incorporation of Pb in the Deposition of Pb(Zr,Ti)O_3 Films by DC Magnetron Reactive Sputtering
- Investigation of Pt/Ti Bottom Electrodes for Pb(Zr, Ti)O_3 Films
- Most Efficient Alternative Manner of Patterning sub-80nm Contact Holes and Trenches with 193nm Lithography
- Structural and Electrical Properties of Lead-Zirconate-Titanate Thin Films Prepared by Multitarget Reactive DC Magnetron Cosputtering
- Ru/TiO_2/ZrO_2/TiN (RIT-TiO_2/ZrO_2) Capacitor Structure for the 50nm DRAM Device and beyond
- Investigation of Ru/TiN Bottom Electrodes Prepared by Chemical Vapor Deposition
- Innovative Al Damascene Process for Nanoscale Interconnects
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Rugged Metal Electrode (RME) for High Density Memory Devices : Surfaces, Interfaces, and Films
- Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65nm Technology Nodes
- Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition
- Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
- Control of Microscratches in Chemical-Mechanical Polishing Process for Shallow Trench Isolation
- Double-Patterning Technique Using Plasma Treatment of Photoresist
- Hot-Spot Detection and Correction Using Full-Chip-Based Process Window Analysis
- Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
- Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition
- A New Optical Film with Antismudge Function and High Durability
- Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance
- Innovative Al Damascene Process for Nanoscale Interconnects
- Highly Reliable 0.15 μm/14 F2 Cell Ferroelectric Random Access Memory Capacitor Using SrRuO3 Buffer Layer
- Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography
- Investigation of Ru/TiN Bottom Electrodes Prepared by Chemical Vapor Deposition
- Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes