Double-Patterning Technique Using Plasma Treatment of Photoresist
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概要
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The double-patterning process was investigated for line-and-space (L/S) patterns of 65 nm half pitch [$k_{1}=0.286$, 0.85-numerical aperture (NA) ArF dry system] by plasma treatment of photoresist (PR). The sequence of this patterning is exposure–plasma treatment–exposure–etching. Si thin-film passivation and HBr plasma treatment (HPT) were applied, and Si thin-film passivation is preferred to HPT in terms of intermixing prevention and etch selectivity. For planarization of the topographic surface, a thick bottom PR was coated on the pattern after the first exposure. Si thin-film passivation and the thick bottom PR enabled the second exposure to be separated from the first exposure. After the etching process was completed down to the nitride hardmask material, the L/S patterns of 65 nm half pitch were achieved at the full-chip level by virtue of the Si thin-film passivation and thick bottom PR. In the meantime, considering the layout characteristic and process flexibility, layout decomposition and the optical proximity correction (OPC) process were performed. Even though the 65 nm half pitch is defined to be such that $k_{1}=0.286$, it is believed that this double patterning scheme we suggested can be applied at the minimum pitch over the theoretical limit below 0.25. Consequently, it is expected that the double-patterning technique (DPT) process will have an important role in the extremely low $k_{1}$ lithography beyond the 32 nm node.
- 2007-09-30
著者
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Moon Joo-tae
Process Development Team Memory Division Samsung Electronics Co. Ltd.
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Cho Han-ku
Process Development Team Semiconductor R&d Center Samsung Electronics
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LEE Doo-Youl
Process Development Team, Semiconductor R&D Center, Samsung Electronics
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Lee Suk-Joo
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Kang Yool
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Chae Yun-Sook
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Kang Yool
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Lee Doo-Youl
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Cho Han-Ku
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Moon Joo-Tae
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Chae Yun-Sook
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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