Chung U-in | Process Development Team Memory Division Samsung Electronics Co. Ltd.

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概要

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著作論文

Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes
Integration of Ferroelectric Random Access Memory Devices with Ir/IrO_2/Pb(Zr_xTi_)O^^_3/Ir Capacitors Formed by Metalorganic Chemical Vapor Deposition-Grown Pb(Zr_xTi_)O_3
Performance and Reliability of MIM (Metal-Insulator-Metal) Capacitors with ZrO_2 for 50nm DRAM Application
Improvement of Contact Resistance between Ru Electrode and TiN Barrier in Ru/Crystalline-Ta_2O_5/Ru Capacitor for 50nm Dynamic Random Access Memory
Investigation of CVD-Co Silicidation for the Improvement of Contact Resistance
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65nm Technology Nodes
Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
Control of Microscratches in Chemical-Mechanical Polishing Process for Shallow Trench Isolation
Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition
Investigation of Chemical Vapor Deposition (CVD)-Derived Cobalt Silicidation for the Improvement of Contact Resistance
Innovative Al Damascene Process for Nanoscale Interconnects
Highly Reliable 0.15 μm/14 F2 Cell Ferroelectric Random Access Memory Capacitor Using SrRuO3 Buffer Layer
Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

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