Chung U-in | Semiconductor R & D Center Samsung Electronics Co.ltd.

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著作論文

Performance and Reliability of MIM (Metal-Insulator-Metal) Capacitors with ZrO_2 for 50nm DRAM Application
Improvement of Contact Resistance of Ru electrode/TiN barrier at Ru/Crystalline-Ta_2O_5/Ru Capacitor for 50nm DRAM device
Investigation of CVD-Co Silicidation for the Improvement of Contact Resistance
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
3D Cell Structure for Low Power and High Performance DRAM : FCAT (Fin-Channel-Array Transistor)(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
3D Cell Structure for Low Power and High Performance DRAM : FCAT (Fin-Channel-Array Transistor)(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Stress Behavior of High Density Plasma Chemical Vapor Deposition Oxide Deposited on a Metal-Patterned Wafer
Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric
The Origin of Micro-Loading Effect of TEOS-O3 Oxide II
Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric

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