Choi Siyoung | Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.

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SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
Formation of High-Temperature Stable Co-Silicide from Co_Ta_/Si Systems
The Formation of High Temperature Stable Co-Silicide from Co_Ta_x/Si Systems
A Study on the Germano-Silicide Formation in the Ni/Si_Ge_x System for CMOS Device Applications
FEOL Process for Sub-100nm DRAM
FEOL Process for Sub-100nm DRAM
Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques

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