Formation of High-Temperature Stable Co-Silicide from Co_<0.92>Ta_<0.08>/Si Systems
スポンサーリンク
概要
- 論文の詳細を見る
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 2001-04-01
著者
-
KANG Ho-Kyu
Process Development Team, Semiconductor R&D Division, Samsung Electronics Co.
-
Choi Siyoung
Process Development Team, Memory Division, Semiconductor Business, Samsung Electronics Co., Ltd.
-
Ko Dae-hong
Department Of Ceramic Engineering Yonsei University
-
Oh Sang-ho
Pohang University Of Science And Technology (postech)
-
LEE Deok-Hyung
Department of Ceramic Engineering, Yonsei University
-
KU Ja-Hum
Process Development Team Semiconductor R&D Division, Samsung Electronics Ltd.
-
FUJIHARA Kazuyuki
Process Development Team Semiconductor R&D Division, Samsung Electronics Ltd.
-
PARK Chan-Gyung
Pohang University of Science and Technology (POSTECH)
-
LEE Hoo-Jeung
Stanford University
-
Kang H‐k
Samsung Electronics Co. Ltd. Kyungki‐do Kor
-
Kang Ho-kyu
Process Development Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kang Ho-kyu
Samsung Electronics Co. Semiconductor R&d Center Memory Process Development Team 2
-
Kang Ho-kyu
Ls Process Development Group Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kang Ho-kyu
Process Development Team Semiconductor R&d Division Samsung Electronics Ltd.
-
Ku Ja-hum
Process Development Team Semiconductor R&d Division Samsung Electronics Ltd.
-
Lee Deok-hyung
Department Of Ceramic Engineering Yonsei University
-
Choi S
Samsung Electronics Co. Ltd. Kyunggi‐do Kor
-
Choi Siyoung
Process Development Team Semiconductor R&d Division Samsung Electronics Ltd.
-
Choi Siyoung
Process Development Team Memory Division Samsung Electronics Co. Ltd.
-
Fujihara Kazuyuki
Process Development Team Semiconductor R&d Division Samsung Electronics Ltd.
-
KU Ja-Hum
Process Development Team Semiconductor R&D Division Samsung Electronics Co.
-
FUJIHARA Kazuyuki
Process Development Team Semiconductor R&D Division Samsung Electronics Co.
関連論文
- Enhanced Retention Characteristics of Pb(Zr, Ti)O_3 Capacitors by Ozone Treatment : Electrical Properties of Condensed Matter
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
- Formation of High-Temperature Stable Co-Silicide from Co_Ta_/Si Systems
- The Formation of High Temperature Stable Co-Silicide from Co_Ta_x/Si Systems
- Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process
- Evaluation of PECVD a-SiC:H as a Cu Diffusion Barrier Layer of Cu Dual Damascene Process
- A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device
- A Novel and Low Thermal Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured HSQ (Hydrogen Silsesquioxane) in STC (Stacked Capacitor) DRAM
- Fabrication and Electrical Characterization of Pt/(Ba, Sr)TiO_3/Pt Capacitors for Ultralarge-Scale Integrated Dynamic Random Access Memory Applications
- The Study on the Reaction Mechanism of HDP-SiOF Film and Inter-Metal-Dielectric Application
- The Study on the Reaction Mechanism of HDP-SiOF Film and Inter-Metal-Dielectric Application
- Fast EM Evaluation by Highly Accelerated Current Density
- Fast EM Evaluation by Highly Accelerated Current Density
- Fast EM Evaluation by Highly Accelerated Current Density
- Integration of Hydrogen Silsesquioxane(HSQ) as an Intermetal Dielectric(IMD)Material for 0.35_ Technology
- Integration of Hydrogen Silsesquioxane (HSQ) as an Intermetal Dielectric (IMD) Material for 0.35μm Technology
- A Study on the Germano-Silicide Formation in the Ni/Si_Ge_x System for CMOS Device Applications
- Deposition and Electrical Characterization of Very Thin SrTiO_3 Films for Ultra Large Scale Integrated Dynamic Random Access Memory Application
- Electrical Characterizations of Pt/(Ba,Sr)TiO_3/Pt Planar Capacitors for ULSI DRAM Applications
- W-Plug Common Contact with CoSi_2 Ohmic Layer for Scaled DRAM and Merged DRAM in Logic (MDL) Devices
- Application of PECVD-WNx Electrode for Ta_2O_5 Capacitor
- Application of PECVD-WNx Electrode for Ta_2O_5 Capacitor
- Ni Germano-Salicide Technology for High Performance MOSFETs
- Ni Germano-Salicide Technology for High Performance MOSFETs
- FEOL Process for Sub-100nm DRAM
- FEOL Process for Sub-100nm DRAM
- Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric
- Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
- Invited Ni Germano-Salicide Technology for High Performance MOSFETs (2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices(AWAD 2001))
- Performance of DRAM Cell Transistor with Thermal Desorption Silicon Etching (TDSE) and Selective Si Channel Epi Techniques
- Channel Strain Measurement of Si
- Channel Strain Measurement of Si_C_x Structures : Effects of Gate Length, Source/Drain Length, and Source/Drain Elevation