Channel Strain Measurement of Si
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概要
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This study examined the dimensional effects on the channel strain in transistor structures with epitaxial Si<inf>1-x</inf>C<inf>x</inf>stressors embedded in the source/drain region using both nanobeam diffraction and finite element simulations. The sizes of the gate and source/drain exerted a strong influence on the channel strain but in opposite directions: While declining linearly with decreasing source/drain length, the channel strain increases at an escalating rate with decreasing gate length. For source/drain elevation, its effects on the channel strain were found to be quite limited to the top surface region; however, this elevation method could be more effective for short-channel transistors.
- 2013-06-25
著者
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Ko Dae-hong
Department Of Ceramic Engineering Yonsei University
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Kim Jae-Hyun
Graduate School of EEWS, KAIST, Daejeon 305-701, Korea
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Lee Hoo-Jeong
Department of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon, Gyeonggi 440-746, Korea
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Kim Sun-Wook
Department of Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea
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Byun Dae-Seop
Department of Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea
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Jung Mijin
Department of Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea
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Chopra Saurabh
Front End Products Group, Applied Materials Inc., Sunnyvale, CA 94085, U.S.A.
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Kim Yihwan
Front End Products Group, Applied Materials Inc., Sunnyvale, CA 94085, U.S.A.
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Han Seung-Min
Graduate School of EEWS, KAIST, Daejeon 305-701, Korea
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