Ni Germano-Salicide Technology for High Performance MOSFETs
スポンサーリンク
概要
- 論文の詳細を見る
Ni salicide process is applied directly on poly-Si_<0.8>Ge_<0.2> gate, and MOSFETs utilizing Ni(Si_XGe_<1-X>/poly-Si_<0.8>Ge_<0.2> gate is fully characterized. The excellent value(〜5Ω/□) of sheet resistance is achieved from 0.15μm Ni(Si_XGe_<1-X>)/Si_<0.8>Ge_<0.2> gae, while Co salicide process applied on Si_<0.8>Ge_<0.2> gate results in R_s fail due to Ge segregation. With poly-Si_<0.8>Ge_<0.2> gate and Ni salicide process, the current drivability of pMOSFETs is significantly improved due to less gate poly depletion and lower source-to-drain resistance(R_<sd>). Conclusively, Ni salicide is the exclusive process for successful germanosilicide of formation on poly-Si_<0.8>Ge_<0.2> gate without poly-Si buffer layer and Ni(Si_XGe_<1-X>)/poly-Si_<0.8>Ge_<0.2> gate can increase I_<dsat> of pMOSFETs by 20% as compared to conventional CoSi_2/poly-Si gate structure.
- 社団法人電子情報通信学会の論文
- 2001-06-28
著者
-
Moon J‐t
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Moon Joo-tae
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Moon Joo
Process Development Team Memory Division Samsung Electronics Co. Ltd.
-
Kang H‐k
Samsung Electronics Co. Ltd. Kyungki‐do Kor
-
Kang Ho-kyu
Process Development Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kang Ho-kyu
Samsung Electronics Co. Semiconductor R&d Center Memory Process Development Team 2
-
Kang Ho-kyu
Ls Process Development Group Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kang Ho-kyu
Process Development Team Semiconductor R&d Division Samsung Electronics Ltd.
-
Ku Ja-hum
Process Development Team Semiconductor R&d Division Samsung Electronics Ltd.
-
Choi Siyoung
Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Ku J.-H.
Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
Choi C.-J.
Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
Fujihara K.
Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
Kang H.-K.
Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
Moon J.-T.
Semiconductor R&D Division, Samsung Electronics Co., Ltd.
-
Kang Ho-kyu
Process Development Team Semiconductor R&d Division Samsung Electronics Co.
-
Choi C.-j.
Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Ku J.-h.
Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Fujihara K.
Semiconductor R&d Division Samsung Electronics Co. Ltd.
-
Fujihara K.
Semiconductor R&d Center Samsung Electronics Co Ltd.
関連論文
- Challenge to 0.13μm Device Patterning using KrF
- Challenge to 0.13μm Device Patterning using KrF
- Challenge to 0.13μm Device Patterning using KrF
- Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes
- Integration of Ferroelectric Random Access Memory Devices with Ir/IrO_2/Pb(Zr_xTi_)O^^_3/Ir Capacitors Formed by Metalorganic Chemical Vapor Deposition-Grown Pb(Zr_xTi_)O_3
- Enhanced Retention Characteristics of Pb(Zr, Ti)O_3 Capacitors by Ozone Treatment : Electrical Properties of Condensed Matter
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
- 3D Cell Structure for Low Power and High Performance DRAM : FCAT (Fin-Channel-Array Transistor)(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- 3D Cell Structure for Low Power and High Performance DRAM : FCAT (Fin-Channel-Array Transistor)(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Formation of High-Temperature Stable Co-Silicide from Co_Ta_/Si Systems
- The Formation of High Temperature Stable Co-Silicide from Co_Ta_x/Si Systems
- Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process
- Evaluation of PECVD a-SiC:H as a Cu Diffusion Barrier Layer of Cu Dual Damascene Process
- A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device
- A Novel and Low Thermal Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured HSQ (Hydrogen Silsesquioxane) in STC (Stacked Capacitor) DRAM
- Fabrication and Electrical Characterization of Pt/(Ba, Sr)TiO_3/Pt Capacitors for Ultralarge-Scale Integrated Dynamic Random Access Memory Applications
- The Study on the Reaction Mechanism of HDP-SiOF Film and Inter-Metal-Dielectric Application
- The Study on the Reaction Mechanism of HDP-SiOF Film and Inter-Metal-Dielectric Application
- Innovative Al Damascene Process for Nanoscale Interconnects
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Optimum TiSi_2 Ohmic Contact Process for Sub-100nm Devices
- Fast EM Evaluation by Highly Accelerated Current Density
- Fast EM Evaluation by Highly Accelerated Current Density
- Fast EM Evaluation by Highly Accelerated Current Density
- Integration of Hydrogen Silsesquioxane(HSQ) as an Intermetal Dielectric(IMD)Material for 0.35_ Technology
- Integration of Hydrogen Silsesquioxane (HSQ) as an Intermetal Dielectric (IMD) Material for 0.35μm Technology
- A Study on the Germano-Silicide Formation in the Ni/Si_Ge_x System for CMOS Device Applications
- Deposition and Electrical Characterization of Very Thin SrTiO_3 Films for Ultra Large Scale Integrated Dynamic Random Access Memory Application
- Electrical Characterizations of Pt/(Ba,Sr)TiO_3/Pt Planar Capacitors for ULSI DRAM Applications
- W-Plug Common Contact with CoSi_2 Ohmic Layer for Scaled DRAM and Merged DRAM in Logic (MDL) Devices
- Application of PECVD-WNx Electrode for Ta_2O_5 Capacitor
- Application of PECVD-WNx Electrode for Ta_2O_5 Capacitor
- Effects of Step Coverage, Cl Content and Deposition Temperature in TiN Top Electrode on the Reliability of Ta_2O_5 and Al_2O_3 MIS Capacitor for 0.13μm Technology and Beyond
- Ni Germano-Salicide Technology for High Performance MOSFETs
- Ni Germano-Salicide Technology for High Performance MOSFETs
- Elimination of Al Line and Via Resistance Degradation under HTS Test in the Application of F-Doped Oxide as Intermetal Dielectrics
- Surface Analysis for Selective SiO_2 Etching by Reflectance Photoelastic Modulated Fourier Transform Infrared Spectroscopy : Nuclear Science, Plasmas, and Electric Discharges
- Novel Method of Threshold Voltage Control of Metal Gate CMOSFETs Using Channel Epitaxy
- Invited Ni Germano-Salicide Technology for High Performance MOSFETs (2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices(AWAD 2001))
- Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition
- Investigation of the Contact Resistance between Ti/TiN and Ru in Metal-1/Plate Contacts of Ruthenium Insulator Silicon Capacitor