Challenge to 0.13μm Device Patterning using KrF
スポンサーリンク
概要
- 論文の詳細を見る
The extension of optical lithography to sub-0.15μm design rule(D/R) using high NA KrF scanner and resolution enhancement technique(RET) is being considered because of the delayed ArF lithography technology, so that the development of 0.13μm device which has been accepted as the role of ArF or any post-KrF technologies will be a real challenge to most lithographers and even to the engineers of related technologies such as etch, thin film, CMP, etc.. In this paper, we discuss and predict the status and feasibility of 0.13μm device lithography with KrF refering to the theory and simulation, and then show some critical device patterns exposed with several KrF scanners which are currently available. Results of high NA scanners such as 0.68NA and 0.70NA available in the near future are also included and discussed. In the latter part of this paper, the most critical issues that can be predicted for 0.13μm device lithography are mentioned as requirements. We conclude that the challenge could be surmountable in the near future.
- 社団法人電子情報通信学会の論文
- 1999-07-23
著者
-
Moon J‐t
Process Development Team Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Moon Joo-tae
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Kim In-Sung
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
-
Lee Jung-Hyeon
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
-
Par Joon-Soo
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
-
Cha Dong-Ho
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
-
Cho Han-Ku
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
-
Lee Sang-In
Semiconductor R&D Center, Samsung Electronics Co. Ltd.
-
Lee S‐i
Process Development Team Semiconductor R&d Center Samsung Electronics
-
Moon Joo
Process Development Team Memory Division Samsung Electronics Co. Ltd.
-
Cho Han-ku
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee Sang-in
Process Development Team Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee S
Ajou Univ. Suwon Kor
-
Lee Sang-in
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee Sang-in
Memory Business Division Samsung Electronics Inc.
-
Lee Sang-in
Semiconductor R & D Center Samsung Electronics Co. Ltd.
-
Kim In-sung
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Cha Dong-ho
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee J‐h
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee Jung-hyeon
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Lee Soo
Process Development Team Semiconductor R&d Center Samsung Electronics
-
Par Joon-soo
Semiconductor R&d Center Samsung Electronics Co. Ltd.
-
Park Joon-soo
Semiconductor R&d Center Samsung Electronics Co. Ltd.
関連論文
- Challenge to 0.13μm Device Patterning using KrF
- Challenge to 0.13μm Device Patterning using KrF
- Challenge to 0.13μm Device Patterning using KrF
- Plasma-Assisted Dry Etching of Ferroelectric Capacitor Modules and Application to a 32M Ferroelectric Random Access Memory Devices with Submicron Feature Sizes
- Integration of Ferroelectric Random Access Memory Devices with Ir/IrO_2/Pb(Zr_xTi_)O^^_3/Ir Capacitors Formed by Metalorganic Chemical Vapor Deposition-Grown Pb(Zr_xTi_)O_3
- Enhanced Retention Characteristics of Pb(Zr, Ti)O_3 Capacitors by Ozone Treatment : Electrical Properties of Condensed Matter
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4 Gb DRAM Technologies(Session 7A Silicon Devices IV,AWAD2006)
- SiGe Source and Drain for Performance Boosting of Peripheral PMOS Transistor in High Density 4Gb DRAM Technologies
- 3D Cell Structure for Low Power and High Performance DRAM : FCAT (Fin-Channel-Array Transistor)(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- 3D Cell Structure for Low Power and High Performance DRAM : FCAT (Fin-Channel-Array Transistor)(Session A1 Si Novel Device and Process)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
- Electrical Properties of Crystalline Ta_2O_5 with Ru Electrode
- Electrical Properties of Ru/Ta_2O_5/Ru Capacitor for 1 Giga-Scale DRAMs and Beyond
- The Electrical Properties of Concave-type (Ba,Sr) TiO_3 Capacitors for Advanced Memories
- The Electrical Properties of Concave-type (Ba,Sr) TiO_3 Capacitors for Advanced Memories
- The Electrical Properties of Concave-type (Ba,Sr) TiO_3 Capacitors for Advanced Memories
- Remote Plasma-Assisted Metal Organic Chemical Vapor Deposition of Tantalum Nitride Thin Films with Different Radicals
- Barrier Metal Properties of Amorphous Tantalum Nitride Thin Films between Platinum and Silicon deposited using Remote Plasma Metal Organic Chemical Vapor Method
- Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process
- Evaluation of PECVD a-SiC:H as a Cu Diffusion Barrier Layer of Cu Dual Damascene Process
- A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device
- A Novel and Low Thermal Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured HSQ (Hydrogen Silsesquioxane) in STC (Stacked Capacitor) DRAM
- Al-Reflow Process with a "Cap-Clamp" for Sub-Micron Contact Holes
- Innovative Al Damascene Process for Nanoscale Interconnects
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity
- Optimum TiSi_2 Ohmic Contact Process for Sub-100nm Devices
- Fast EM Evaluation by Highly Accelerated Current Density
- Fast EM Evaluation by Highly Accelerated Current Density
- Fast EM Evaluation by Highly Accelerated Current Density
- Effects of Step Coverage, Cl Content and Deposition Temperature in TiN Top Electrode on the Reliability of Ta_2O_5 and Al_2O_3 MIS Capacitor for 0.13μm Technology and Beyond
- Ni Germano-Salicide Technology for High Performance MOSFETs
- Ni Germano-Salicide Technology for High Performance MOSFETs
- Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric
- The Origin of Micro-Loading Effect of TEOS-O3 Oxide II
- Surface Analysis for Selective SiO_2 Etching by Reflectance Photoelastic Modulated Fourier Transform Infrared Spectroscopy : Nuclear Science, Plasmas, and Electric Discharges
- Monte Carlo Simulation Study of Local Critical Dimension Error on Mask and Wafer
- Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition
- Investigation of the Contact Resistance between Ti/TiN and Ru in Metal-1/Plate Contacts of Ruthenium Insulator Silicon Capacitor
- Elimination of Al Line and Via Resistance Degradation under HTS Test in Application of F-Doped Oxide as Intermetal Dielectric
- Monte Carlo Simulation Study of Local Critical Dimension Error on Mask and Wafer